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5/1/2006VTS'061 Upper Bounding Fault Coverage by Structural Analysis and Signal Monitoring Vishwani D. Agrawal Auburn University, Dept. of ECE, Auburn,

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Presentation on theme: "5/1/2006VTS'061 Upper Bounding Fault Coverage by Structural Analysis and Signal Monitoring Vishwani D. Agrawal Auburn University, Dept. of ECE, Auburn,"— Presentation transcript:

1 5/1/2006VTS'061 Upper Bounding Fault Coverage by Structural Analysis and Signal Monitoring Vishwani D. Agrawal Auburn University, Dept. of ECE, Auburn, AL 36849 Soumitra Bose Vijay Gangaram Intel Corporation, Design Technology, Folsom, CA 95630

2 5/1/2006VTS'062 Outline Problem statement and motivation Background Upper bounding algorithm Benchmark results An application: test-point insertion Conclusion

3 5/1/2006VTS'063 Problem Statement and Motivation A fault simulation problem Large non-scan or partial-scan circuits Long functional verification vector sequences Objective: –Find compact high fault coverage vectors for testing –Find test points for DFT Motivation Exact fault simulation is too expensive Statistical fault simulator is a useful tool, but needs accuracy –In coverage estimation –In identifying faults not detectable by vector sequence

4 5/1/2006VTS'064 Background Approximate fault simulation –Per-vector analysis Critical path tracing (CPT), Abramovici et al., IEEE D&T 1984. Necessary conditions, Akers et al., ITC 1990. –Post-simulation analysis, Stafan, Jain and Agrawal, IEEE-D&T 1985. Dominator analysis in ATPG, Kirkland and Mercer, ITC 1987. Fault detection at fanout stem depends on signal states in this part and the observability of the dominator. Fanout stem Dominator

5 5/1/2006VTS'065 Stafan: A Tutorial Example 11001 00110 00000 C0=0.4 C1=0.6 C0=1.0 C1=0.0 C0=0.6, C1=0.4 S=0.6 C0=0.4 C1=0.6 S=1.0 C0=0.4, C1=0.6 (controllabilities) S=0.4 (sensitization count) sa1 sa0 sa1 Detected fault Incorrectly detected faults OB0=1.0 OB1=1.0 OB0=0.0 OB1=1.0 OB0=1.0, OB1=0.0 (observabilities) OB0=1.0 OB1=1.0 OB0=1.0, OB1=0.0 PD: Prob(sa0 detected) = C1 × OB1, Prob(sa1 detected) = C0 × OB0 Threshold detection by N vectors: 1 – (1 – PD) N ≥ 0.5

6 5/1/2006VTS'066 A Circuit Requiring Dynamic Analysis Stem requires vector-specific analysis When only 00 and 11 patterns occur on these lines, the stem will be unobservable Dominator Vector-less static analysis can identify redundant stem faults in the previous example.

7 5/1/2006VTS'067 Upper Bounding Algorithm Structural Analysis For each fanout stem identify dominator set (gates on paths between the stem and its dominator) Based on the inversion parities of paths in the dominator set determine stem observability conditions Monitor Ocurrence of Selected Signal States During Logic Simulation For a gate, set of input states that forbids path sensitization For a fanout stem with all same parity paths, set of off- path signal states that forbids sensitizstion of any path For a fanout stem with different parity paths, set of off- path signal state that simultaneously sensitizes diffrenet parity paths Similar conditions derived for mixed parity paths Total number of conditions: O(2×k×N), k = average fanin of gates, N = number of gates

8 5/1/2006VTS'068 Algorithm: Fanout Reconvergence (I) 11 00 11 00 11 Same vector applied twice: sa0 G2 G3 G5 sa1 Negative errors: G1 output found unobservable. Structural analysis: Stem G1 has two {G2 and G3} same parity paths. Signal monitoring: Only pattern 0XX0 can make stem G1 unobservable  G1 is observable. G1 Portion of c17: Fanout G1 reconverges with same inversion parity at G5. Detected faults not detected by stafan

9 5/1/2006VTS'069 Algorithm: Fanout Reconvergence (II) G0 G2 G4 10 11 10 01 11 10 sa0 00 Positive error: When observable fanouts of I2 are treated as independent. Structural analysis: Fanouts paths {G0, and G1-G2} have different parities. Signal monitoring: Propagation through G0: {I1=1 and (I3=0 or I4=0)} = false Propagation through G1-G2: {(I3=1 and I4=1) and I1=0} = false  I2 is unobservable I1 I2 I3 I4 G1 Portion of c17: Fanout I2 reconverges with different inversion parities at G4. Undetected fault detected by stafan

10 5/1/2006VTS'0610 Results: Benchmark Circuits Circuit Fault coverage (%) CPU % over logic simulation ExactStafan*UB Stafan c43293.1594.8593.3233.3 c88091.0890.0292.0420.0 c135587.9318.7488.8222.2 c190869.7975.7173.1030.8 c267077.2863.4978.5636.8 c354070.7976.2671.9930.8 c531591.7476.5993.6434.9 c628899.7492.9199.7416.4 c755284.4774.5487.9952.2 *Original stafan; different from “vanilla estimate” in the paper, which is an improved stafan.

11 5/1/2006VTS'0611 Fault Coverage of c2670 Error in upper bound estimate varies with coverage: Peak error of about 12% after 8 vectors and 53% coverage.

12 5/1/2006VTS'0612 Application: Scanout Selection Given large functional sets, each with ~10 6 vectors: 1.low individual vector set coverage 2.high cumulative coverage 3.set of potential observation (scanout) points find minimal observation points that maximize coverage. Exact solution: fault simulation with no fault dropping. Conventional fault simulation takes several days. Estimate fault detection status for every fault at every potential observation point. Find a minimal subset of candidates that covers all faults.

13 5/1/2006VTS'0613 Application: Scanout Selection Circuit characteristicsScanout flip-flop selction Name No. of Gates Vector sets Total Flip- flops Max. cov. (%) No. of Scan flip- flops By fault sim.By UB-stafan CPU time Cov. % CPU time Cov. % d1130k22014,54077.62,0008days72.745min74.1 d2180k458,50088.920012days81.41.5hrs85.7 d3494k11212,55078.51,60015days74.04hrs76.8 Note: Fault simulation runtimes assume fault dropping.

14 5/1/2006VTS'0614 Conclusion Estimation errors due to reconverging fanouts: –Positive: Undetected faults estimated as detected. –Negative: Detected faults estimated as undetected. Upper Bounding improvements: –Positive errors reduced by dominators and monitoring –Negative errors reduced by reconvergence analysis –Useful for Test development DFT – test point selection Structural analysis of dominators and signal monitoring can reduce fault detection errors for non-random functional input sequences; to be discussed in a forthcoming paper.

15 5/1/2006VTS'0615 ITC’06: Improved Stafan – Average, and Upper/Lower Bound Estimates

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