1. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Topics n Sequential machine implementation: –clocking. n Sequential machine design.

2. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Clock period n For each phase, phase period must be longer than sum of: –combinational delay; –latch propagation delay. n Phase period depends on longest path.

3. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Unbalanced delays Logic with unbalanced delays leads to inefficient use of logic: long clock periodshort clock period

4. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Retiming Retiming moves memory elements through combinational logic:

5. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Retiming properties n Retiming changes encoding of values in registers, but proper values can be reconstructed with combinational logic. n Retiming may increase number of registers required. n Retiming must preserve number of latches around a cycle - may not be possible with reconvergent fanout.

6. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Advanced performance analysis n Latch-based systems always have some idle logic. n Can increase performance by blurring phase boundaries. Results in cycle time closer to average of phases.

7. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Example with unbalanced phases One phase is much longer than the other:

8. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Spreading out a phase Compute only part of long paths in one phase:

9. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Spreading out a phase, cont. Use other phase for end of long logic block and all of short logic block:

10. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Problems n Hard to debug - can’t stop the system. n Hard to initialize system state. n More sensitive to process variations.

11. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Sequential machine design n Two ways to specify sequential machine: –structure: interconnection of logic gates and memory elements. –function: Boolean description of next-state and output functions. n Best way depends on type of machine being described.

12. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Counter n Easy to specify as one-bit counter. n Harder to specify n-bit counter behavior. Can specify n-bit counter as structure made of 1-bit counters.

13. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR One-bit counter Truth table: countC in nextC out 0000 0110 1010 1101

14. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR One-bit counter implementation

15. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR One-bit counter operation All operations are performed as s  2. n XOR computes next value of this bit of counter. n NAND/inverter compute carry-out.

16. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR One-bit counter sticks l1(latch)n(NAND)i(INV)x(XOR)l2(latch) C in C out V DD V SS 11 11 22 22

17. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR n-bit counter structure

18. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR State transition graphs/tables n Basic functional description of FSM. n Symbolic truth table for next-state, output functions: –no structure of logic; –no encoding of states. n State transition graph and table are functionally equivalent.

19. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR 01 string recognizer Behavior of machine which recognizes “01”in continuous stream of bits: time012345 input001101 statebit1bit2bit2bit1bit1bit2 nextbit2bit2bit1bit1bit2bit1 output001001

20. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR 01 recognizer operation n Waits for 0 to appear in state bit1. n Goes into separate state bit2 when 0 appears. n If 1 appears immediately after 0, can have a 01 on next cycle, so can go back to wait for 0 in state bit1.

21. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR State transition table Symbolic state transition table: inputpresentnextoutput 0bit1bit20 1bit1bit10 0bit2bit20 1bit2bit11

22. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR State transition graph Equivalent to state transition table:

23. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR State assignment n Must find binary encoding for symbolic statesstate assignment. n Choice of state assignment directly affects both the next-state and output logic: –area; –delay. n May also encode some machine inputs/outputs.

24. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR 01 recognizer encoding Choose bit1= 0, bit2 = 1: inputpresentnextoutput 0010 1000 0110 1101

25. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Logic implementation After encoding, truth table can be implemented in gates:

26. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Traffic light controller n Intersection of two roads: –highway (busy); –farm (not busy). n Want to give green light to highway as much as possible. n Want to give green to farm when needed. n Must always have at least one red light.

27. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Traffic light

28. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Communicating sequential machine countersequencer reset short long carshighwayfarm

29. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR System operation n Sensor on farm road indicates when cars on farm road are waiting for green light. n Must obey required lengths for green, yellow lights.

30. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Traffic light machine n Build controller out of two machines: –sequencer which sets colors of lights, etc. –timer which is used to control durations of lights. n Separate counter isolates logical design from clock period. n Separate counter greatly reduces number of states in sequencer.

31. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Sequencer state transition graph hwy- green farm- green hwy- yellow farm- yellow (cars & long) / 0 green red cars & long / 1 green red short / 0 yellow red short / 1 yellow red cars & long / 0 green red cars?& long / 1 green red short / 0 red yellow short/ 1 red yellow