1. The Design of a Low-Power High-Speed Phase Locked Loop Tiankuan Liu 1, Datao Gong 1, Suen Hou 2, Zhihua Liang 1, Chonghan Liu 1, Da-Shung Su 2, Ping-Kun Teng 2, Annie C. Xiang 1, Jingbo Ye 1 1 Department of Physics, Southern Methodist University, Dallas TX 75275, U.S.A. 2 Institute of Physics, Academia Sinica, Nangang 11529, Taipei, Taiwan liu@mail.physics.smu.edu

2. 2 Outline Introduction PLL Design –Block diagram –Layout –VCO design and simulation –Divider design and simulation PLL performances –Acquisition time –Deterministic jitter –Random jitter Conclusion Acknowledgments

3. 3 Introduction PresentUpgrade Data rate per front-end board (FEB) (Gbps)1.6100 Power consumption per Gbps (mW)118890 ATLAS Liquid Argon Calorimeter Optical Link Upgrade Silicon-on-Sapphire (SoS) CMOS technology –High speed, low power, high quality inductors, no latch-up –The radiation tolerance of a commercial 0.25 µm SoS CMOS technology has been evaluated in the previous study Design Goals: –Operation frequency: 4 ~ 5 GHz for data rate 8 ~ 10 Gbps –Random jitter < 1 ps (RMS) –Power consumption < 100 mW Application background

4. 4 PLL Design: Block Diagram LVDS Receiver is the input interface CML driver is used to drive 50 Ω coaxial cables Phase frequency detector Test points 2 nd order passive Low pass filter with programmable bandwidth charge pump with programmable current (20, 40, 60, 80 µA) LC-tank based voltage controlled oscillator (VCO) Divider (divide by 16)

5. 5 PLL Design: Shared Blocks The LVDS receiver, the phase frequency detector (PFD), the charge pump, the pass filter, the CMOS divider, and the CML driver are shared with the 5 Gbps 16:1 serializer. For details of these design blocks please see the poster “A 16:1 serializer for data transmission at 5 Gbps” presented by Dr. Datao Gong at TWEPP, Paris France, September, 2009. The bandwidth of the low pass filter and the current of charge pump are programmable to suit different applications. The loop bandwidth and the phase margin are calculated in the following table. Configuration C 0 C 1 C 2 001010100 BW (MHz) phase margin (deg) BW (MHz) phase margin (deg) BW (MHz) phase margin (deg) Charge pump gain (µA) 200.4246.330.8446.341.6846.33 400.7256.291.4456.302.8856.31 601.0259.502.0459.504.0859.53 801.3159.992.6359.995.2560.04

6. 6 PLL Design: Layout Area 1.4 mm x 1.7 mm

7. 7 PLL Design: VCO VCO TypeLC-tank based VCO Ring oscillator- based VCO Power ConsumptionLowHigh FrequencyHighLow Phase noise/jitter performanceGoodBad Radiation sensitivitySmallLarge Tuning rangeNarrowWide Chip areaLargeSmall Comparison of two common type VCOs

8. 8 PLL Design: VCO Schematic Start-up circuit Reference current source On-chip spiral inductors with a peak frequency of 5.1 GHz. The Q factor is simulated to be 21.2 at 5 GHz. Decoupling capacitors are used to improve the noise performance Cross-coupled transistors provides negative resistance, compensating the energy loss in the LC tank A NMOS or PMOS transistor with its source and drain tied together serves a varactor with monotonic C-V curve and large tuning range (Cmax/Cmin > 2).

9. 9 PLL Design: VCO Simulation The tuning range is 3.79 – 5.01 GHz at the typical corner and room temperature and varies less than 8% in all corners and temperature range.

10. 10 PLL Design: Dividers The divider consists of a CML divider (divide by 2), a CML to CMOS converter, and a CMOS divider (divide by 8) The dividers can work up to 5.1 GHz at all corners from -40 °C to 85 °C

11. 11 PLL Design: CML Divider

12. 12 PLL Design: CML to CMOS Converter

13. 13 PLL Performances: Acquisition Time The PLL tracks the input frequency and phase after 9 µs

14. 14 PLL Performances: Deterministic Jitter The deterministic jitter after tracking (9 µs) is less than 2 ps (peak- peak)

15. 15 PLL Performances: Random Jitter The random jitter due to the VCO’s phase noise, the dominant noise source, is less than 1 ps (RMS) from 10 kHz to 100 MHz The phase noise of the VCO in the worst case

16. 16 Conclusion: Simulated Results of the PLL Tuning range (GHz)3.78 – 5.01 power consumption (core PLL mW)104 Area (including pads and decoupling caps, mm 2 )1.4 x 1.7 Random Jitter from VCO (RMS, ps)< 1 Deterministic jitter after locking (peak-peak, ps)2 Acquisition time (μs)9

17. 17 Conclusion: Status and Plan Fabrication: submitted on August 3, 2009; Chip delivery: November 28, 2009 Test: in lab test: December 15, 2009; Radiation test: February - March, 2010 Plan: apply this LC-based PLL and design a multi- channel 16:1 serializer with each channel working around 10 Gbps in 2011

18. 18 Acknowledgments Grant: US-ATLAS R&D program for the upgrade of the LHC and the US Department of Energy grant DE-FG02-04ER41299. Peter Clarke, Jay Clementson, Yi Kang, Francis M. Rotella, John Sung, and Gary Wu from Peregrine Semiconductor Corporation for technical assistance. Justin Ross at Southern Methodist University for setting up and maintaining the software environment. Jasoslav Ban, Mauro Citterio, Christine Hu, Sachin Junnarkar, Valentino Liberali, Paulo Rodrigues Simoes Moreira, Mitch Newcomer, Quan Sun, Fukun Tang, and Carla Vacchi for technical assistance and reviewing of this design.