1. 1 Performed By: Khaskin Luba Einhorn Raziel Einhorn Raziel Instructor: Rivkin Ina Spring 2004 Spring 2004 Virtex II-Pro Dynamical Test Application Part A --

2. 2 Quick Overview Examining possible space-compatibility of civilian devices, in order to integrate them in satellites. Examining possible space-compatibility of civilian devices, in order to integrate them in satellites. Statistically modeling the device ’ s robustness to temporary damage and it ’ s ability to recover in a case of an error. Statistically modeling the device ’ s robustness to temporary damage and it ’ s ability to recover in a case of an error. Testing the device under real-time radiation. Testing the device under real-time radiation.

3. 3 The System FPGA Device (Vitex II-Pro)

4. 4 System Block Diagram DUT Virtex II-Pro Evaluation Board (platform) Host JTAG Port USB Port Xilinx Tools GUI Hyper Terminal LogicPower PC

5. 5 DLP-USB245M Module Leds, Push-Buttons JTAG Port LCD RIO Ports Virtex II-Pro P130 Module DIP Switches DUT – Device Under Test – Virtex II-Pro Evaluation Board DUT Host

6. 6 The Virtex II-Pro – Closer look Specifications: Configurable logic block (CLB) 18Kb Block-RAMs 44 18X18 bit multipliers 4 2.5 Gbps Rocket I/O transceivers 4 Digital Clock Manager units (DCM) Power-PC 4.05 CPU DUT Host

7. 7 Graphical User Interface User transparent User transparent Initializing the testing system Initializing the testing system Choosing and loading the testing function Choosing and loading the testing function Receiving data via USB and calculating statistical results Receiving data via USB and calculating statistical results GUI was created in C++ language, using Visual Studio 6 GUI was created in C++ language, using Visual Studio 6 Uses supplied Dynamic Library files (Dll files) Uses supplied Dynamic Library files (Dll files) In order to control the USB module In order to control the USB module DUT Host

8. 8 Graphical User Interface - Algorithm Test in Process Gathering test info Writing appropriate impl. file Test type decision Opening USB port Sending start signal Listening to USB Collecting data to Excel file Closing USB port Delete temporary var. End Test condition Opening Excel START Test Ended DUT Host

9. 9 GUI – Main Window Status Window Test Type Tests List DUT Host

10. 10 GUI – Settings Window Programs ’ location USB connection & drivers check button DUT Host

11. 11 DLP-USB245M - Features Fast connection – up to 1 Mb/sec. Fast connection – up to 1 Mb/sec. Small implementation Small implementation Simple Interface Simple Interface Mounted on a P130 expansion module Mounted on a P130 expansion module DUT Host

12. 12 The Testing Concept

13. 13 The Testing System Flow End Test Command Creating input and comparison vectors; Updating control signals Listening to Host Single/ Multiple tests? Waiting for outputs Sending input vectors to MUT Multiple tests Checking outputs; Sending results Single test Loading bit file Test Ended

14. 14 MUT - Module Under Test The examined modules: I/O Blocks I/O Blocks Fast Multipliers Fast Multipliers Rocket I/O Rocket I/O Digital Clock Manager (DCM) Digital Clock Manager (DCM) CLB Memory CLB Memory CLB Flop-flops CLB Flop-flops CLB logic CLB logic BRAMs BRAMs Power-PC Power-PC USB Contr. MCT MUT

15. 15 USB Controller USB Contr. MCT MUT Controls reading and writing cycles. Controls reading and writing cycles. Determines USB ’ s control signals during reading and writing cycles. Determines USB ’ s control signals during reading and writing cycles. Sets up the relevant data to be sent back to host. Sets up the relevant data to be sent back to host. Designed with minimal usage of logic and memory elements. Designed with minimal usage of logic and memory elements.

16. 16 USB Controller USB Contr. MCT MUT

17. 17 MCT Identical basic structure for all the testing functions: Identical basic structure for all the testing functions: - Defines input and comparison vectors in order to test module ’ s functionality. - Defines input and comparison vectors in order to test module ’ s functionality. - Computes the statistical number of errors and instructs their transference using the USB Controller. - Computes the statistical number of errors and instructs their transference using the USB Controller. Designed with the ambition to maximize the test ’ s mapping of each examined module. Designed with the ambition to maximize the test ’ s mapping of each examined module. Minimal usage of logic and memory elements. Minimal usage of logic and memory elements. USB Contr. MCT MUT

18. 18 Example – Fast Multipliers USB Controller MUT MCT USB Contr. MCT MUT

19. 19 Example – Fast Multipliers Several blocks of fast multipliers are chained together to achieve 100% mapping. Several blocks of fast multipliers are chained together to achieve 100% mapping. The input vectors, set by the MCT, diffuse through the multipliers chain. The outputs are being compared with the expected result vectors using several feedbacks. The input vectors, set by the MCT, diffuse through the multipliers chain. The outputs are being compared with the expected result vectors using several feedbacks. The calculated errors are being sent via USB, using the USB Controller, in steady time intervals. The calculated errors are being sent via USB, using the USB Controller, in steady time intervals. USB Contr. MCT MUT

20. 20 Design Tools HDL Designer – Creating hardware applications HDL Designer – Creating hardware applications MODELSIM – VHDL simulation MODELSIM – VHDL simulation Synplify – Synthesis tool Synplify – Synthesis tool Xilinx ISE Project Navigator – Place and Route Xilinx ISE Project Navigator – Place and Route Visual C++ – Designing the GUI Visual C++ – Designing the GUI

21. 21 Part B - Schedule Implementing tests for the remainder modules Implementing tests for the remainder modules Learning about PPC & Rocket I/O Learning about PPC & Rocket I/O Learning EDK, Architecture Wizard Learning EDK, Architecture Wizard Implementing Power-PC tests Implementing Power-PC tests Implementing Rocket I/O tests Implementing Rocket I/O tests Implementing Special logic tests (e.g. one loop tests, various user- controllable tests, etc.) Implementing Special logic tests (e.g. one loop tests, various user- controllable tests, etc.) Redesigning the GUI application respectively. Redesigning the GUI application respectively.

22. 22 Summary and conclusions First part goals – complete system framework, including test implementation, USB connection and application design – have been successfully achieved First part goals – complete system framework, including test implementation, USB connection and application design – have been successfully achieved The initially planned communication channel has been changed from Serial port (UART) to USB port The initially planned communication channel has been changed from Serial port (UART) to USB port