1. E-Voting Machine - Design Presentation Group M1 Bohyun Jessica Kim Jonathan Chiang Chi Ho Yoon Donald Cober Mon. Oct 13th Beginning Gate Level Layout Secure Electronic Voting Terminal

2. Updated Transistor Counts Structural Verilog Entire System Gate-level Layout More Layout Refining Floorplan Status Update

3. Data Bus Machine Init FSM User ID FSM Selectio n FSM Confirm ation FSM Display User ID SRAM Message ROM Card Reader Fingerprint Scanner Encryption Key SRAM User Input Write-in SRAM Choice SRAM TX_Check Selection Counter Key Register XOR 8 bit Full Adder 8 bit Full Adder 8 bit Full Adder 8 bit Full Adder XOR 8 bit MUX 01 01 01 8 bit Add/Sub 01 8 bit MUX T: 128 8-bit REG T: 88 8-bit REG COMMS Register Shift Registe r In Shift Registe r Out constant init

4. Changes during structural FSM Encoding: – FSMs with 6, 12, 7 and 9 states – Binary encoding has about the same transistor count as One-hot encoding – One-hot is much easier to layout Address Counter – SRAM data is accessed sequentially – Address registers are linked as counters – Counters can increment, decrement, and reset – Requires an additional type of register

6. Full adder layout

8. XOR layout

10. Behavioral Verilog Transistor Counts BlockStatesAddressRegisters Distinct Outputs RandomTransistors Machine Init FSM62 bits5550105 User ID FSM123 bits713130207 Selection FSM72 bits5990145 Confirmation FSM96 bits10880170

11. Optimized Gate Layout Transistor Counts BlockState Register T Address Counter T RandomTotal Machine Init FSM544638138 User ID FSM10870102280 Selection FSM634668177 Confirmation FSM819262235

12. Structural Verilog Transistor Counts BlockOldTotal Message ROM28080 Selection Counter3358 TX_Check3386 User Input244422 COMMs13231860 BlockOldTotal Key SRAM228 Write-in SRAM3 596 User ID SRAM454 Choice SRAM228