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Lecture 11: MOS Transistor

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1 Lecture 11: MOS Transistor
Prof. Niknejad

2 Lecture Outline Review: MOS Capacitors Regions
CV Curve Threshold Voltage MOS Transistors (4.1 − 4.3): Overview Cross-section and layout I-V Curve Department of EECS University of California, Berkeley

3 Body (p-type substrate)
MOS Capacitor Oxide (SiO2) Body (p-type substrate) Gate (n+ poly) Very Thin! MOS = Metal Oxide Silicon Sandwich of conductors separated by an insulator “Metal” is more commonly a heavily doped polysilicon layer n+ or p+ layer NMOS  p-type substrate, PMOS  n-type substrate Department of EECS University of California, Berkeley

4 Accumulation: VGB < VFB
+ Body (p-type substrate) −−−−−−−−−−−−−−−−−− Essentially a parallel plate capacitor Capacitance is determined by oxide thickness: Department of EECS University of California, Berkeley

5 Depletion: VFB<VGB < VT
+ Body (p-type substrate) − − − − − − − − − − − − − − − − − Positive charge on gate terminates on negative charges in depletion region Potential drop across the oxide and depletion region Charge has a square-root dependence on applied bias Department of EECS University of California, Berkeley

6 Body (p-type substrate)
Inversion + Body (p-type substrate) − − − − − − − − − − − − − − − − − The surface potential increases to a point where the electron density at the surface equals the background ion density At this point, the depletion region stops growing and the extra charge is provided by the inversion charge at surface Department of EECS University of California, Berkeley

7 Threshold Voltage The threshold voltage is defined as the gate-body voltage that causes the surface to change from p-type to n-type For this condition, the surface potential has to equal the negative of the p-type potential Apply KCL around loop: + Gate (n+ poly) − − − − − − Department of EECS University of California, Berkeley

8 Inversion Stops Depletion
A simple approximation is to assume that once inversion happens, the depletion region stops growing This is a good assumption since the inversion charge is an exponential function of the surface potential Under this condition: Department of EECS University of California, Berkeley

9 Q-V Curve for MOS Capacitor
inversion accumulation depletion In accumulation, the charge is simply proportional to the applies gate-body bias In inversion, the same is true In depletion, the charge grows slower since the voltage is applied over a depletion region Department of EECS University of California, Berkeley

10 Numerical Example MOS Capacitor with p-type substrate:
Calculate flat-band: Calculate threshold voltage: Department of EECS University of California, Berkeley

11 Num Example: Electric Field in Oxide
Apply a gate-to-body voltage: Device is in accumulation The entire voltage drop is across the oxide: The charge in the substrate (body) consist of holes: Department of EECS University of California, Berkeley

12 Numerical Example: Depletion Region
In inversion, what’s the depletion region width and charge? Department of EECS University of California, Berkeley

13 MOS CV Curve Small-signal capacitance is slope of Q-V curve
Capacitance is linear in accumulation and inversion Capacitance is depletion region is smallest Capacitance is non-linear in depletion Department of EECS University of California, Berkeley

14 C-V Curve Equivalent Circuits
In accumulation mode the capacitance is just due to the voltage drop across tox In inversion the incremental charge comes from the inversion layer (depletion region stops growing). In depletion region, the voltage drop is across the oxide and the depletion region Department of EECS University of California, Berkeley

15 MOSFET Cross Section Add two junctions around MOS capacitor
gate body source drain diffusion regions p+ n+ p-type substrate n+ Add two junctions around MOS capacitor The regions forms PN junctions with substrate MOSFET is a four terminal device The body is usually grounded (or at a DC potential) For ICs, the body contact is at surface Department of EECS University of California, Berkeley

16 MOSFET Layout poly gate contact G B S G D B S D p-type substrate p+ n+ n+ Planar process: complete structure can be specified by a 2D layout Design engineer can control the transistor width W and L Process engineer controls tox, Na, xj, etc. Department of EECS University of California, Berkeley

17 PMOS & NMOS A MOSFET by any other name is still a MOSFET:
G G p-type substrate n+ S D B p+ n-type substrate p+ S D B n+ NMOS PMOS A MOSFET by any other name is still a MOSFET: NMOS, PMOS, nMOS, pMOS NFET, PFET IGFET Other flavors: JFET, MESFET CMOS technology: The ability to fabricated NMOS and PMOS devices simultaneously Department of EECS University of California, Berkeley

18 CMOS Complementary MOS: Both P and N type devices
G G n+ S D B p+ B S D n-type well n+ p+ p+ NMOS PMOS p-type substrate Complementary MOS: Both P and N type devices Create a n-type body in a p-type substrate through compensation. This new region is called a “well”. To isolate the PMOS from the NMOS, the well must be reverse biased (pn junction) Department of EECS University of California, Berkeley

19 Circuit Symbols The symbols with the arrows are typically used in analog applications The body contact is often not shown The source/drain can switch depending on how the device is biased (the device has inherent symmetry) Department of EECS University of California, Berkeley

20 Observed Behavior: ID-VGS
Current zero for negative gate voltage Current in transistor is very low until the gate voltage crosses the threshold voltage of device (same threshold voltage as MOS capacitor) Current increases rapidly at first and then it finally reaches a point where it simply increases linearly Department of EECS University of California, Berkeley

21 Observed Behavior: ID-VDS
non-linear resistor region “constant” current resistor region For low values of drain voltage, the device is like a resistor As the voltage is increases, the resistance behaves non-linearly and the rate of increase of current slows Eventually the current stops growing and remains essentially constant (current source) Department of EECS University of California, Berkeley

22 “Linear” Region Current
S D p+ n+ p-type n+ Inversion layer “channel” NMOS If the gate is biased above threshold, the surface is inverted This inverted region forms a channel that connects the drain and gate If a drain voltage is applied positive, electrons will flow from source to drain Department of EECS University of California, Berkeley

23 MOSFET “Linear” Region
The current in this channel is given by The charge proportional to the voltage applied across the oxide over threshold If the channel is uniform density, only drift current flows Department of EECS University of California, Berkeley

24 MOSFET: Variable Resistor
Notice that in the linear region, the current is proportional to the voltage Can define a voltage-dependent resistor This is a nice variable resistor, electronically tunable! Department of EECS University of California, Berkeley


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