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3. 3 "design productivity crisis“:

4. 4 --hardware capability increases at a rapid rate --to harness this capability, we must employ design reuse, "IP" (intellectual property), abstraction --we need "smarter" tools to allow us to succeed at this task some current strategies and emerging trends:

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7. 7 TRANSISTOR (PHYSICAL) LIBRARY COMPONENT (PHYS. / BEHAV./ STRUCT.) NETLIST (STRUCTURAL) n1: a b o1 n2: a c o2 n3: o1 o2 o3 --VHDL ARCHITECTURE (STRUCTURAL) architecture A of HALFADDER is component XOR port (X1,X2: in bit; O: out bit); end component; component AND port (X1,X2: in bit; O: out bit); end component; begin G1: XOR port map (A,B,S); G2: AND port map (A,B,COUT); end A; Example (half adder, based on Figure 4, Chapter 13, Handbook of Mechatronics and additions) --VHDL entity entity HALFADDER is port (A,B: in bit; S,COUT: out bit); end ADDER; --VHDL ARCHITECTURE (BEHAVIORAL) architecture CONCURRENT of HALF ADDER is --this is a behavioral description ("delay" = 5 ns here) --it does NOT imply that XOR or AND gates will be used in the implementation begin S <= (A xor B) after 5 ns; COUT <= (A and B) after 5 ns; end CONCURRENT; --VHDL ARCHITECTURE (BEHAVIORAL/DATAFLOW): architecture PROCESS_BEHAVIOR of HALF ADDER is begin SUM_PROC: process(A,B) begin if (A = B) then S <= '0' after 5 ns; else S<= (A or B) after 5 ns; end if; end process SUM_PROC; CAR_PROC: process (A,B) begin case A is when '0' => COUT <= A after 5 ns; when '1' => COUT <= B after 5 ns; when others => COUT <= 'X' after 5 ns; end case; end process CAR_PROC; end PROCESS_BEHAVIOR;

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10. 10 --VHDL entity entity HALFADDER is port (A,B: in bit; S,COUT: out bit); end ADDER; --VHDL ARCHITECTURE (BEHAVIORAL) architecture CONCURRENT of HALF ADDER is --this is a behavioral description ("delay" = 5 ns here) --it does NOT imply that XOR or AND gates will be used in the implementation begin S <= (A xor B) after 5 ns; COUT <= (A and B) after 5 ns; end CONCURRENT; --VHDL ARCHITECTURE (BEHAVIORAL/DATAFLOW): architecture PROCESS_BEHAVIOR of HALF ADDER is begin SUM_PROC: process(A,B) begin if (A = B) then S <= '0' after 5 ns; else S<= (A or B) after 5 ns; end if; end process SUM_PROC; CAR_PROC: process (A,B) begin case A is when '0' => COUT <= A after 5 ns; when '1' => COUT <= B after 5 ns; when others => COUT <= 'X' after 5 ns; end case; end process CAR_PROC; end PROCESS_BEHAVIOR;

11. 11 --VHDL entity entity HALFADDER is port (A,B: in bit; S,COUT: out bit); end ADDER; --VHDL ARCHITECTURE (STRUCTURAL) architecture A of HALFADDER is component XOR port (X1,X2: in bit; O: out bit); end component; component AND port (X1,X2: in bit; O: out bit); end component; begin G1: XOR port map (A,B,S); G2: AND port map (A,B,COUT); end A;

12. 12 TRANSISTOR (PHYSICAL)

13. 13 In this course we will be working mostly at the BEHAVIORAL and STRUCTURAL levels. We will rely on the Altera design tools to do MOST of the physical design and optimization. Here we will quickly review the basic STRUCTURAL building blocks commonly used-- complete sets, muxes, demuxes, adders, flip-flops, counters, registers, memory, I/O.

14. 14 Complete Sets. In some situations it is efficient to represent all Boolean functions in terms of a (small) set of fundamental functions. For example, if we are building hardware devices, it would make our work easier if we could just design two or three different ones and then build everything else out of these few. Such a set is called a complete set. For Boolean functions of two variables, there are three complete sets that are commonly used: a. AND, OR, NOT b. NAND c. NOR Using properties of boolean algebra, it can be shown that a complete set for two inputs will also be a complete set for any number of inputs. this fact will turn out to be especially useful when we consider physical implementations of these functions.

15. 15 Proof that AND,OR, NOT is complete for 2-input boolean functions: we can give a straightforward truth table proof of this fact. For n > 2, how big does our truth table need to be? If we have N inputs, A1,…,AN, then each Ai, 1 <= i <= N, can take on two values, 0 or 1, so there are 2 N rows in an N-input truth table. A Boolean function of A1,…,AN is defined by assigning a 0 or 1 value to each row. So there must be 2**(2 N ) possible functions. For N = 2, there are 2**(2 2 ) = 2**4 = 16. We get the following table: AB f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd fe ff 00 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 01 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 10 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 11 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 and we can represent functions f0--ff as follows: f0=A(~A) f1=AB f2=A(~B) f3=A f4=(~A)B f5=B f6=A(~B)+(~A)B f7=A+B f8=~(A+B) f9=(~A)(~B)+AB fa=(~B) fb=A+(~B) fc=~A fd=(~A)+B fe=~(AB) ff=A+(~A) The representation is not necessarily unique, e.g., f0 = A AND ~A = B AND ~B

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