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Design of RF CMOS Low Noise Amplifiers Using a Current Based MOSFET Model Virgínia Helena Varotto Baroncini Oscar da Costa Gouveia Filho
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OUTLINE 1. Introduction 2. MOSFET Model 3. High-Frequency Noise Model 4. LNA Analysis 5. LNA Design Example 6. Conclusion
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Introduction Submicrometer CMOS technology allows the integration of RF circuits. Low voltage and low power operation → moderate inversion Model valid from weak to strong inversion
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MOSFET MODEL S D B G I(V G,V S ) I(V G,V D ) I F = forward current I R = reverse current
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Normalized currents where are the normalized currents andis the normalization current
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Operation Regions of the MOS transistor irir ifif 10 -3 10 -1 1 10 0 10 2 10 3 10 -3 10 -1 10 0 10 2 10 3 forward saturation i f > 100 i r reverse saturation i r > 100 i f strong weak moderate strong moderate weak triode
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Small signal parameters Transconductances Capacitances
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High- Frequency Noise Model S vRg S ig S id RgRg C gb C gs g ms V sb g m V gb B B S S G D
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Channel Thermal Noise 10 -3 10 -2 10 -1 10 0 10 1 10 2 10 3 10 -29 10 -28 10 -27 10 -26 10 -25 10 -24 10 -23 ifif S id (A 2 /Hz)
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Induced Gate Noise
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LNA Analysis LSLS LgLg LdLd V in VbVb V DD M1M1 M2M2 Cascode LNA with inductive source degeneration
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Impedance Matching LgLg LsLs C gb C gs g mb V sb g ms V gs Z in Z1Z1 Z 1 can be viewed as the parallel of a resistor R with the capacitance Cgs
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Simplified small signal model for the LNA matching is achieved simply by making the real part of Z in equal to the source resistance and its imaginary part equal to zero.
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Noise Figure LNA small-signal model for noise calculations Definition The noise figure can be expressed as a function of i f
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Noise figure versus W/L for several inversion levels at 2.5 GHz
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LNA Design Example Resonance frequency2,5 GHz Supply voltage2,5 V Length 0,35 m Source resistance 50 Noise Figure< 2dB LNA Design Parameters
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1. Choice of the inversion level i f =35 Procedure
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2. L s for impedance matching
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3. Transistor width for minimum noise figure Noise figure versus W/L for several inversion levels at 2.5 GHz
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4. L g to satisfy the resonance frequency 5. L d to adjust the gain and the output resonance frequency
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LNA Design Results W/LWIDID RsRs LsLs LgLg LdLd 1500 525 m 4,1 mA 50 0,7 nH7,6 nH2,5 nH LsLs LgLg LdLd RSRS CLCL R Ld M1M1 M2M2 V out V in + V bias V DD
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Simulation results Input impedance
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Noise Figure
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Conclusions The main advantage of this methodology is that is valid in all regions of the operation of the MOS transistors; It is possible to move the operation point of RF devices from strong inversion to moderate inversion taking advantage of higher gm/ID ratio, without degrading the noise figure;
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