1. 1/27/06EECS150 Lab Lecture #21 Designing with Verilog EECS150 Spring 2006 – Lab Lecture #2 Brian Gawalt Greg Gibeling

2. 1/27/06EECS150 Lab Lecture #22 Today Top-Down and Bottom-Up Partitioning & Interfaces Behavioral vs. Structural Verilog Administrative Info Blocking and Non-Blocking Verilog and Hardware Lab #2 Primitives

3. 1/27/06EECS150 Lab Lecture #23 Top-Down vs. Bottom-Up (1) Top-Down Design Start by defining the project Then break it down Starts here:

4. 1/27/06EECS150 Lab Lecture #24 Top-Down vs. Bottom-Up (2) Top-Down Design Ends here:

5. 1/27/06EECS150 Lab Lecture #25 Top-Down vs. Bottom-Up (3) Bottom-Up Testing Faster, Easier and Cheaper Test each little component thoroughly Allows you to easily replicate working components

6. 1/27/06EECS150 Lab Lecture #26 Partitioning & Interfaces (1) Partitioning Break the large module up Decide what sub-modules make sense Partitioning is for your benefit It needs to make sense to you Each module should be: A reasonable size Independently testable Successful partitioning allows easier collaboration on a large project

7. 1/27/06EECS150 Lab Lecture #27 Partitioning & Interfaces (2) Interfaces A concise definition of signals and timing Timing is vital, do NOT omit it Must be clean Don’t send useless signals across Bad partitioning might hinder this An interface is a contract Lets other people use/reuse your module

8. 1/27/06EECS150 Lab Lecture #28 Behavioral vs. Structural (1) Rule of thumb: Behavioral doesn’t have sub-components Structural has sub-components: Instantiated Modules Instantiated Gates Instantiated Primitives Most modules are mixed Obviously this is the most flexible

9. 1/27/06EECS150 Lab Lecture #29 Behavioral vs. Structural (2)

10. 1/27/06EECS150 Lab Lecture #210 Behavioral vs. Structural (3)

11. 1/27/06EECS150 Lab Lecture #211 Administrative Info Lab Grading Get it in by the opening of the next lab Partial credit will be given for incomplete labs Please stick to one lab session Card Key Access for All is coming soon!

12. 1/27/06EECS150 Lab Lecture #212 Blocking vs. Non-Blocking (1) always @ (a) begin b = a; c = b; end always @ (posedge Clock) begin b <= a; c <= b; end C = B = A B = Old A C = Old B Verilog FragmentResult

13. 1/27/06EECS150 Lab Lecture #213 Blocking vs. Non-Blocking (2) Use Non-Blocking for FlipFlop Inference posedge/negedge require Non-Blocking Else simulation and synthesis wont match Use #1 to show causality always @ (posedge Clock) begin b <= #1 a; c <= #1 b; end

14. 1/27/06EECS150 Lab Lecture #214 Blocking vs. Non-Blocking (3) If you use blocking for FlipFlops: YOU WILL NOT GET WHAT YOU WANT! always @ (posedge Clock) begin b = a; // b will go away c = b; // c will be a FlipFlop end // b isn’t needed at all always @ (posedge Clock) begin c = b; // c will be a FlipFlop b = a; // b will be a FlipFlop end

15. 1/27/06EECS150 Lab Lecture #215 Blocking vs. Non-Blocking (4) file xyz.v: module XYZ(A, B, Clock); inputB, Clock; outputA; regA; always @ (posedge Clock) A = B; endmodule file abc.v: module ABC(B, C, Clock); inputC, Clock; outputB; regB; always @ (posedge Clock) B = C; endmodule Race Conditions THIS IS WRONG

16. 1/27/06EECS150 Lab Lecture #216 Blocking vs. Non-Blocking (5) file xyz.v: module XYZ(A, B, Clock); inputB, Clock; outputA; regA; always @ (posedge Clock) A <= B; endmodule file abc.v: module ABC(B, C, Clock); inputC, Clock; outputB; regB; always @ (posedge Clock) B <= C; endmodule Race Conditions THIS IS CORRECT

17. 1/27/06EECS150 Lab Lecture #217 Verilog and Hardware (1) assign Sum = A + B; reg [1:0]Sum; always @ (A or B) begin Sum = A + B; end

18. 1/27/06EECS150 Lab Lecture #218 Verilog and Hardware (2) assign Out = Select ? A : B; reg [1:0]Out; always @ (Select or A or B) begin if (Select) Out = A; else Out = B; end

19. 1/27/06EECS150 Lab Lecture #219 Verilog and Hardware (3) assign Out = Sub ? (A-B) : (A+B); reg [1:0]Out; always @ (Sub or A or B) begin if (Sub) Out = A - B; else Out = A + B; end

20. 1/27/06EECS150 Lab Lecture #220 Verilog and Hardware (4) reg [1:0]Out; always @ (posedge Clock) begin if (Reset) Out <= 2’b00; else Out <= In; end

21. 1/27/06EECS150 Lab Lecture #221 Lab #2 (1) Lab2Top Accumulator Stores sum of all inputs Written in behavioral verilog Same function as Lab1Circuit Peak Detector Stores largest of all inputs Written in structural verilog

22. 1/27/06EECS150 Lab Lecture #222 Lab #2 (2)

23. 1/27/06EECS150 Lab Lecture #223 Lab #2 (3) Accumulator.v

24. 1/27/06EECS150 Lab Lecture #224 Lab #2 (4) PeakDetector.v

25. 1/27/06EECS150 Lab Lecture #225 Primitives (1) wireSIntermediate, SFinal, CPropagrate, CGenerate; xorxor1(SIntermediate,In,Out); andand1(CGenerate,In,Out); xorxor2(SFinal,SIntermediate,CIn); andand2(CPropagate,In,CIn); oror1(COut,CGenerate,CPropagate); FDCEFF(.Q(Out),.C(Clock),.CE(Enable),.CLR(Reset),.D(SFinal));

26. 1/27/06EECS150 Lab Lecture #226 Primitives (2) wireSIntermediate, SFinal, CPropagrate, CGenerate; xorxor1(SIntermediate,In,Out); andand1(CGenerate,In,Out); xorxor2(SFinal,SIntermediate,CIn); andand2(CPropagate,In,CIn); oror1(COut,CGenerate,CPropagate); FDCEFF(.Q(Out),.C(Clock),.CE(Enable),.CLR(Reset),.D(SFinal));

27. 1/27/06EECS150 Lab Lecture #227 Primitives (3) wireSIntermediate, SFinal, CPropagrate, CGenerate; xorxor1(SIntermediate,In,Out); andand1(CGenerate,In,Out); xorxor2(SFinal,SIntermediate,CIn); andand2(CPropagate,In,CIn); oror1(COut,CGenerate,CPropagate); FDCEFF(.Q(Out),.C(Clock),.CE(Enable),.CLR(Reset),.D(SFinal));