1. 1 Lucas-Lehmer Primality Tester Presentation 8 March 22nd 2006 Team: W-4 Nathan Stohs W4-1 Brian Johnson W4-2 Joe Hurley W4-3 Marques Johnson W4-4 Design Manager: Prateek Goenka Overall Objective: Modular Arithmetic unit with a creative use

2. 2 Status Finished –Project Chosen –C simulations –Behavioral Verilog –Structural Verilog –Floor Plan –Schematics –Pathmill Simulation of Top Level In Progress –Layout –Layout Simulations To Do –More Layout/Simulations

3. 3 Transistor Counts ModuleTransistor Count Count2,664 Mod_Multiply11,006 Mod_Add1,168 Partial Products8,676 Register896 Sub_16704 Compare36 Mod_P1,280 Register896 Counter266 FSM700 Total17,286

4. 4 Sub_16

5. 5 Shift Left

6. 6 Mod Add

7. 7 Mod Add Schematic

8. 8 Mod Add Simulation 127 + 68 Mod 127 = 69

9. 9 Block Area Estimates (Updated) ModuleArea (μm 2 ) Count13,200 Partial Product38,000 Sub 163,500 Compare200 ModP5,600 Register4,000 Mod_add6,528 FSM3,000

10. 10 Updated Floorplan

11. 11 Partial Product Progress BlocksInstancesStatus Sub163DRC/LVS/sim Shift Left250% Layout Shift Right250% Layout Mux162DRC/LVS Logic (~200 transistors) 10% Layout FullAdder161DRC/LVS

12. 12 Overall Status BlocksInstancesStatus Mod Add1DRC/LVS/sim ModP (shifter)150% Layout Sub 161DRC/LVS/sim FSM/Count10% Layout Register20% Layout Compare10% Layout

13. 13 What’s Next Continue Layout Continue Simulating Layout Power Estimations on Layout Change Design of Registers Optimize

14. 14 Questions?