1. DRAM Design By Arlen Cox Dec 9, 2002 ECPE 131

3. Sense Amplifier

4. Address Decoder

5. Write Operation 1 2 3 1. Set Word Line High 2. Precharge Cell 3. Add/Subtract Charge from Cell

6. Write Continued Storage Capacitor Precharge Write “1” Final Value Storage Capacitor Precharge Write “0” Final Value

7. Read Operation 1 2 3 4 5 6 7 1. Precharge Amp 2. Set Read Line High 3. Set Word Line High 4. Balance Charges 5. Begin Amplification 6. Force to High or Low 7. Read to Output

8. Read Continued Read “0” Storage Amp Read “1” Storage Amp

9. Write/Read “1” Precharge Write Precharge Read Storage Cap Vbit /Vbit

10. Write/Read “0” Precharge Write Precharge Read Storage Cap /Vbit Vbit

11. *Simplified DRAM simulation *Input buffer M199IN0VDDVDDpmos W=30u L=1.5u M209IN000nmos W=30u L=1.5u M2119VDDVDDpmos W=30u L=1.5u M221900nmos W=30u L=1.5u *WR tristate M11WR20nmos W=30u L=1.5u *DRAM Cell M22W030nmos W=30u L=1.5u C130100p *RD tristate M82RD80nmos W=30u L=1.5u *Sense Amplifier M354VDDVDDpmos W=30u L=1.5u M6785VDDpmos W=30u L=1.5u M7875VDDpmos W=30u L=1.5u M117860nmos W=30u L=1.5u M128760nmos W=30u L=1.5u M136S00nmos W=30u L=1.5u C270200p C380100p *S inverter M44SVDDVDDpmos W=30u L=1.5u M54S00nmos W=30u L=1.5u *Precharge Circuit M147P80nmos W=30u L=1.5u M157PVDD20nmos W=30u L=1.5u M168PVDD20nmos W=30u L=1.5u *Output Tristate M238OE110nmos W=30u L=1.5u *Output Buffer M91011VDDVDDpmos W=30u L=1.5u M10101100pmos W=30u L=1.5u M17Out010VDDVDDnmos W=30u L=1.5u M18Out01000nmos W=30u L=1.5u *Constant Voltage sources VCCVDD0DC 5V VCC2VDD20DC 2.5V *Transistor Models.MODEL nmos NMOS(VTO=1 LAMBDA=0.067 KP=50E-6).MODEL pmos PMOS(VTO=1 LAMBDA=0.067 KP=50E-6) *initial conditions for capacitors to 0.IC v(7)=0V v(8)=0V *Input Signals *write from 0 to 500ns *read from 500ns to 1000ns VIn0IN00PWL(0V 0V 1ns 0V) VSS0PWL(0V 0V 700ns 0V 701ns 5V) VPP0PWL(0V 0V 1ns 5V 200ns 5V 201ns 0V 500ns 0V 501ns 5V 700ns 5V 701ns 0V) VRDRD0PWL(0V 0V 1ns 5V 200ns 5V 201ns 0V 500ns 0V 501ns 5V 800ns 5V 801ns 0V) VWRWR0PWL(0V 0V 200ns 0V 201ns 5V 300ns 5V 301ns 0V) VOEOE0PWL(0V 0V 900ns 0V 901ns 5V) VW0W00PWL(0V 0V 1ns 5V 300ns 5V 301ns 0V 700ns 0V 701ns 5V 800ns 5V 801ns 0V) *Close.END SPICE Code Input Buffer DRAM Cell Amplifier Precharge Circuit Output Buffer MOSFET Model Input Signals

12. References ● Howe, Sodini Microelectronics an Integrated Approach 1997 Prentice Hall ● Keith, Baker, DRAM Circuit Design a Tutorial 2000 IEEE Press ● http://www.eng.abdn.ac.uk/~eng186/spice/ SPICE Manual

13. Thanks ● Dr. Khoie – Circuit Design Help/SPICE Help/Encouragement ● Dr. Schroeder – SPICE Expertise ● UC Berkeley CAD Group ● Georgia Tech Research Institute ● University of Ljubljana – SPICE Opus Simulator