1. Design and Implementation of VLSI Systems (EN0160) Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Weste/Addison Wesley]

2. Last time: Lecture 04: CMOS Gate Layout CMOS Fabrication http://www.appliedmaterials.com/HTMAC/animated.html http://www.appliedmaterials.com/HTMAC/animated.html Today: CMOS Gate Layout

3. Summary of Terminology body diffusion (n/p) source drain well tap contact metal track via polysilicon gate length/width gate oxide channel  All these structures must obey the dimensions and separation rules dictated by the process fabrication facility

4. Process design rules Design rules change from fab to fab Fab examples: IBM, Intel, TI, TSMC, UMC, MOSIS Design rules change according to the process technology

5. Lambda rules Feature Size: minimum distance between source and drain of transistor Feature size = 2λ (@ 90nm feature size λ=45) According to Moore’s Law, how much does the feature size scale by every ~2 years?

6. Design rules and gate layout Lambda rules are conservative

7. More design rules

8. More and more design rules

9. Inverters with taps

10. Layout of a 3-input NAND gate

11. Stick diagrams No need to be drawn to scale

12. Pitch of routing tracks

13. Gate area estimation

14. First Assignment Exercises –1.6, 1.8, 1.12, 1.16, 1.18 Code of ethics: –You can discuss with your colleagues –You cannot copy from your colleagues/web/printed material –Assignments are to be done individually –Cheating will not be tolerated