1. Presenter : Yeh Chi-Tsai System-on-chip validation using UML and CWL Qiang Zhu 1, Ryosuke Oish 1, Takashi Hasegawa 2, Tsuneo Nakata 1 1 Fujitsu Laboratories LTD., 2 Fujitsu Limited Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, 2004

2. Presenter : Yeh Chi-Tsai Integrating UML into SoC design process Qiang Zhu 1, Ryosuke Oish 1, Takashi Hasegawa 2, Tsuneo Nakata 1 1 Fujitsu Laboratories LTD., 2 Fujitsu Limited Design, Automation and Test in Europe, 2005

3. Presenter : Yeh Chi-Tsai System-on-Chip Verification Process Using UML Qiang Zhu 1, Tsuneo Nakata 1, Masataka Mine 2, Kenichiro Kuroki 3,Yoichi Endo 3, and Takashi Hasegawa 3 1 Fujitsu Laboratories LTD., 2 Fujitsu Cadtech Limited, 3 Fujitsu Limited UML 2004 Satellite Activities, LNCS 3297, pp. 138 – 149, 2005.

4. 4 Outline  Abstract  Motivation  Verification Strategy for SoC ◦ Modeling Functionality Using UML ◦ Modeling Communication Using CWL ◦ Validating Functionality of Components ◦ Validating Communication of Components  Applying for a Media Processing SoC  Conclusions and Future Work

5. 5 Abstract  In these papers, we propose a verification methodology for System-On-Chip (SoC) design using Unified Modeling Language (UML). We introduce UML as a formal model to analyze and formalize the specification. The specification validation and implementation verification can be performed systematically by introducing UML.  We applied our method to a Mobile Media Processors SoC. We improved the quality of the specification written in informal natural language through UML modeling techniques. The test scenarios and coverage metrics for implementation are derived from the UML model systematically.  The result shows that our proposal is effective for eliminating errors from both specification and implementation.

6. 6 Outline  Abstract  Motivation  Verification Strategy for SoC ◦ Modeling Functionality Using UML ◦ Modeling Communication Using CWL ◦ Validating Functionality of Components ◦ Validating Communication of Components  Applying for a Media Processing SoC  Conclusions and Future Work

7. 7 Motivation  What’s the problem? ◦ With the increasing complexity of hardware-software heterogeneous systems such as SoC, we have to face two crises in SoC design. The design crisis is caused by design productivity gap due to chip complexity growing 58% but design productivity currently growing 21% annually. This means the current SoC design methodology cannot adapt to the growth of complexity of SoC. ◦ We have to face another crisis for SoC design, named verification crisis. According to our experiences, more than 70% period of the SoC development lifecycle is used to verify the correctness of the design. Nevertheless, despite a huge effort of verification, most of chips must respin once or twice after they released. Unfortunately, each chip respin usually costs hundreds of thousands dollars. This indicates we need a new verification process for SoC development.

8. 8 Why chooses UML  In the software community, Object-Oriented Analysis and Design (OOAD) techniques can help designers to seamlessly integrate the result of analysis into the implementation. UML is employed as a modeling language to characterize the results of analysis and design obviously, clearly and comprehensively.  In SoC design, HDL such as VHDL, Verilog are programming languages for implementing hardware at the RTL. SystemC is a C++ library proposed to make an executable model from the algorithmic level to the RTL level. An object- oriented design process for system-on-chip using UML and SystemC is proposed through extending UML notation. Such techniques tend to concentrate on the design process and make an effort to depart from RTL to the behavior levels.

9. 9 Proposed approach (1)  We propose a novel design and verification process from high-level specifications to RTL implementations using the Unified Modeling Language (UML), Component Wrapper Language (CWL) and SystemC.

10. 10 Proposed approach (2)  The key strategies of our approach are: ◦ Refining the design from requirements analysis to the RTL implementation incrementally. ◦ Integrating validation and verification processes not only for the RTL implementation, as well as for the specification based on formalized UML and CWL models. Fig. 2. Integrating UML into SoC Design Process

11. 11 Outline  Abstract  Motivation  Verification Strategy for SoC ◦ Modeling Functionality Using UML ◦ Modeling Communication Using CWL ◦ Validating Functionality of Components ◦ Validating Communication of Components  Applying for a Media Processing SoC  Conclusions and Future Work

12. 12 Verification Strategy for SoC  The verification strategy focuses on the structure of SoC. We emphasize three levels of verification: ◦ (1) Components functionality ◦ (2) Components communication ◦ (3) Chip-level integration

13. 13 Outline  Abstract  Motivation  Verification Strategy for SoC ◦ Modeling Functionality Using UML ◦ Modeling Communication Using CWL ◦ Validating Functionality of Components ◦ Validating Communication of Components  Applying for a Media Processing SoC  Conclusions and Future Work

14. 14 Modeling Functionality Using UML  We employ UML to model such information captured from specification and validate that there are no incompleteness, inconsis- tency errors in the specifi- cation.  Fig. 3 shows the modeling flow that translates the specification into an UML model. Fig. 3. UML modeling flow from specification

15. 15 Use Case Analysis (1)  Use Case Analysis captures users, functions, and their relationships using use case diagrams.  Fig. 4 depicts an example of a use case diagram. Actors in use case diagrams describe the external components who want to utilize functions of the target component. Fig. 4. An example of use case diagram

16. 16 Use Case Analysis (2)  We must know how actors use such functions. The usages of use case are represented by clarifying event flows among the target component and its associated actors.  The event flow for a use case is written in natural language, namely use case description. Table 1 shows an example of use case description.  In use case descriptions, we must clarify the following items for each use case: precondition, post- condition, basic path, alternative path, and exceptional path respectively.

17. 17 Table 1. Use case descriptions

18. 18 Static Analysis  Concentrate on the structure and data types that appear in the specification.  We use UML class diagrams to describe them and their relationships.  We stipulate there are two types of classes in SoC specifications. (Fig. 5.) ◦ Control class represents components ◦ Data type class that appears in input/output events.

19. 19 Fig. 5. An example of class diagrams

20. 20 Dynamic Analysis  Capture a system-level behavior by considering the input/output events in event flows for each use case.  We use UML sequence diagrams and state chart diagrams to describe behaviors of the target component.  We use sequence diagrams to formalize event flows in use case descriptions written in natural language. The events in use case descriptions can be modeled with operations of a class.  State chart diagrams can help us find the paths of event flow that are not listed in use case descriptions. This lets us validate whether the specification or UML model is complete or not.

21. 21 Fig. 6. Sequence diagrams

22. 22 Fig. 7. State chart diagrams

23. 23 Outline  Abstract  Motivation  Verification Strategy for SoC ◦ Modeling Functionality Using UML ◦ Modeling Communication Using CWL ◦ Validating Functionality of Components ◦ Validating Communication of Components  Applying for a Media Processing SoC  Conclusions and Future Work

24. 24 Modeling Communication Using CWL  We need a specification description for modeling the communication between the input and output ports of a component at the signal level. Unfortunately, we have not found a proper notation to model such properties efficiently in UML.  Component Wrapper Language (CWL) has been proposed to model the interface protocol of IP cores. We introduce CWL to model the communication protocol among components.  The communication protocols are divided into the atomic transactions that are used from operations (events) modeled in sequence diagrams in the UML model as a method call. The CWL model translates such method call into the signal-level communications.

25. 25 Outline  Abstract  Motivation  Verification Strategy for SoC ◦ Modeling Functionality Using UML ◦ Modeling Communication Using CWL ◦ Validating Functionality of Components ◦ Validating Communication of Components  Applying for a Media Processing SoC  Conclusions and Future Work

26. 26 Validating Functionality of Components  We adopt two strategies for validating the functionality of components in our verification process: ◦ Validating the UML model to find errors in the specification due to incompleteness and inconsistency. ◦ Verifying the implementation using test scenarios and functional coverage metrics that are derived from the UML model.

27. 27 The completeness of specification  The completeness of use case indicates that use cases must cover all functions in specification and each function in specification must be used by a use case once, at least.  The completeness of event flow indicates that the listed paths of event flow include all possible scenarios that can occur in a use case.

28. 28 The consistency of specification  The consistency between a use case and its event flows indicates all normal paths (basic path, alternative path) of event flows in a use case can reach the given post-condition under the pre-condition defined in a use case description.  The consistency among UML diagrams indicates there are no violations among UML diagrams.

29. 29 The test scenarios from UML  The test scenarios at use case level must cover all use cases from the use case diagram.  The test scenarios at event flow level can be extracted from all paths of event flow include basic, alternative and exceptional paths from sequence diagrams.  The test scenarios at parameter level can be extracted from class diagrams and their constraints.

30. 30 Fig. 8. Deriving test scenarios from UML model

31. 31 Outline  Abstract  Motivation  Verification Strategy for SoC ◦ Modeling Functionality Using UML ◦ Modeling Communication Using CWL ◦ Validating Functionality of Components ◦ Validating Communication of Components  Applying for a Media Processing SoC  Conclusions and Future Work

32. 32 Validating Communication of Components  For validating the correctness of communications among components, we generate an HDL protocol checker from the CWL description using CWL2HDL tool. We insert the protocol checker among components to check whether there are any protocol violations of communications during functional validation of the implementation.  W integrate them into a chip level verification. In chip integration testing, we also derive test scenarios and functional coverage from the UML model captured from a chip level specification to confirm the correctness of the specification as well as the implementation.

33. 33 Outline  Abstract  Motivation  Verification Strategy for SoC ◦ Modeling Functionality Using UML ◦ Modeling Communication Using CWL ◦ Validating Functionality of Components ◦ Validating Communication of Components  Applying for a Media Processing SoC  Conclusions and Future Work

34. 34 Overview of the MMPs

35. 35 Verification Process for MMPs  Designers developed the chip based on traditional design style: determining the chip level specifications, making the component specifications and their communication specifications, then implementing them into the HDL source code. Debugging the implementation and white box verification for each component was performed as usual. All specifications created by designers are written in natural language.  The verification team analyzed specification and translated them into UML and CWL respectively. While the verification team found errors due to incompleteness, inconsistency in the UML & CWL model, the verification team confirmed such errors with the designers to eliminate them from the specification or the UML & CWL model. After validation of the specification, the verification team derived test scenarios from the UML model to validate the implementation of components, communications, and chip integration with the black box verification.

36. 36 Application Results  We took 6 months and 12 verification engineers to validate the specification and perform black box verification for each component, communication, and chip integration. Note that there was only one experienced verification engineer in verification team.  Designers were responsible for white box test of each component and guaranteed code coverage for each component to reach 100%. The verification team assured functional coverage and transaction coverage for each component reached 100% in black box test. The chip released in about 1.5 months after tape out.

37. 37 Fig. 10 The results for errors and their discovery time 132 errors 40 errors 51 errors 3 errors

38. 38 Table 2. Specification errors for components

39. 39 Table 3. Implementation bugs for components

40. 40 Outline  Abstract  Motivation  Verification Strategy for SoC ◦ Modeling Functionality Using UML ◦ Modeling Communication Using CWL ◦ Validating Functionality of Components ◦ Validating Communication of Components  Applying for a Media Processing SoC  Conclusions and Future Work

41. 41 Conclusions and Future Work  In this paper, we proposed a verification process that integrates UML and CWL to validate the functionality and communication protocols for SoC. We applied our method to a Mobile Media Processor developed in Fujitsu. We found 132 errors from the specification and discovered 51 bugs from the implementation using test scenarios and coverage metrics derived from the UML model. The application results show our method is not only helpful to improve the quality of specification, but also useful to eliminate bugs from the implementation efficiently.  In future work, we will develop a tool, which could help us validate the completeness and consistency of the UML model automatically.