1. CSC Muon Trigger September 16, 2003 CMS Annual Review 1 Current Status of CSC Trigger Elements – Quick Summary Jay Hauser, with many slides from Darin Acosta and Stan Durkin n On-chamber u Comparator ASICs for Cathodes (CFEB cards) – DONE. u ALCT Anode Trigger – almost done (~90%) n Peripheral-crate u TMB Trigger Motherboard – pre-production prototypes u MPC Muon Port Card – 2 nd generation prototype u CCB Clock & Control Board – 2 nd generation prototype n Track Finder crate in counting house u SP2002 Sector Processor – 2 nd generation prototype u CSC Muon Sorter – 1 st generation prototype u Backplane – 2 nd generation prototype

2. CSC Muon Trigger September 16, 2003 CMS Annual Review 2 CSC Muon Trigger Scheme CSC CFEB ALCT 1 of 24 CFEB 1 of 2 LVDB 1 of 5 Anode Front-end Board Cathode Front-end Board Anode LCT Board MPCMPC DMBDMB TMBTMB DMBDMB TMBTMB DMBDMB TMBTMB DMBDMB TMBTMB DMBDMB TMBTMB DMBDMB TMBTMB DMBDMB TMBTMB DMBDMB TMBTMB DMBDMB TMBTMB CCBCCB CONTROLLERCONTROLLER Peripheral Crate on iron disk (1 of 60) Trigger Timing & Control CSC Track-Finder Crate (1) Trigger Motherboard (9) DAQ Motherboard (9) Clock Control Board Optical link In underground counting room On detector Muon Portcard (1) EMU part: on-chamber nearing end of production, peripheral crate production > ESR in Nov. ‘03 TriDAS part: Second generation prototypes Trigger Primitives 3-D Track-Finding and Measurement Sector Processor (12) Muon Sorter (1)

3. CSC Muon Trigger September 16, 2003 CMS Annual Review 3 On-chamber CSC Trigger Electronics n Comparator ASICs – DONE. u Compare pulse heights from adjacent strips to find position of muon to ½-strip u 15000 16-channel ASICS on CFEB boards (OSU) n ALCT Boards – nearly DONE. u Finds tracks among anode hits, stores data for readout u 468+spares boards of 3 types (288-, 384-, 672-channel)

4. CSC Muon Trigger September 16, 2003 CMS Annual Review 4 CSC Peripheral Crates in UXC55 MPCMPC DMBDMB TMBTMB DMBDMB TMBTMB DMBDMB TMBTMB DMBDMB TMBTMB DMBDMB TMBTMB DMBDMB TMBTMB DMBDMB TMBTMB DMBDMB TMBTMB DMBDMB TMBTMB CCBCCB CONTROLLERCONTROLLER Clock Control Board (CCB) TRIG Motherboard (TMB) DAQ Motherboard (DMB) Crate Controller Muon Port Card (MPC)

5. CSC Muon Trigger September 16, 2003 CMS Annual Review 5 SP2002 (Main Board) Merged 3 SR2000s Optical Transceivers 16 x 1.6 Gbit/s Links Front FPGA TLK2501 Transceiver Phi Local LUT Eta Global LUT Phi Global LUT VME/ CCB FPGA To/from custom GTLP back- plane Data conversion: Receiver: Florida n 12 Used in CMS System

6. CSC Muon Trigger September 16, 2003 CMS Annual Review 6 SP Trigger Logic From SP2000 to SP2002 mezzanine card (5 manufactured) Xilinx Virtex-2 XC2V4000 ~800 user I/O Performs track-finding logic and P T assignment Florida

7. CSC Muon Trigger September 16, 2003 CMS Annual Review 7 GTLP BACKPLANE INTERFACE MEZZANINE CARD (same as SP design) LVDS DRIVERS AND SCSI-3 CONNECTORS Muon Sorter Rice n Sorts up to 36 muons from 12 SP’s and transmits best 4 to GMT n Have 4 boards in hand, one stuffed (except for backplane interface) n Sorter testing is in progress, will test with Track-Finder in the autumn n Only 1 needed in CMS

8. CSC Muon Trigger September 16, 2003 CMS Annual Review 8 CSC Test Beam Studies 2003 n First structured beam period May 23-June 1 u Trigger primitives tests were highly successful: l Verified peripheral crate electronics design for Nov. ESR u MPC-to-SP optical link data transfer unsuccessful (synch. problems) n Unstructured beam period June 13-28 u Improved low- and high-rate CLCT and TMB studies, angle scans n Second structured beam period Sept. 17-22 u Patches to fix optical link data transfer from MPC to SP u New readout shell program (fully OO software)

9. CSC Muon Trigger September 16, 2003 CMS Annual Review 9 2003 Time-structured Beam Test Setup Peripheral Crate 2 DMB, 2 TMB 1 CCB, 1 MPC FED crate 1 DDU PC TTC crate DAQ Data Trigger primitives S1 S2 S3 beam CSC 1 CSC 2 Track finder Crate TRIDAS n X5A Setup

10. CSC Muon Trigger September 16, 2003 CMS Annual Review 10 CSC Bunch ID From ALCT Timing n First, tune the ALCT data latching in 2 ns intervals (0-32ns) and maximize the single-BX fraction of events: n Then look at the BX distribution relative to BX from scintillator (L1A): n ALCT BX efficiency 98.7%

11. CSC Muon Trigger September 16, 2003 CMS Annual Review 11 CSC Trigger High Rate Tests Expected LCT rate at LHC < 25 KHz (ME1/1) data consistent with dead-time = 225 ns Chamber #1 CLCT 0 500 1,000 1,500 2,000 05001,0001,5002,0002,5003,000 Beam Intensity (KHz) CLCT Rate (KHz)

12. CSC Muon Trigger September 16, 2003 CMS Annual Review 12 CSC Track Finder Test u Successfully passed optical link loopback tests and MPC  SP chain tests using 40 MHz crystal oscillator to drive system u MPC  SP optical link tests failed at the structured beam tests in May 2003 (link errors every few ms) u Clock was derived from TTC system (mi  vi  vx  rx) u Combined clock jitter presumably too large to drive optical links u PLL was not used to clean clock (i.e. QPLL was not available) Sector Processor 2 CSCs

13. CSC Muon Trigger September 16, 2003 CMS Annual Review 13 Additional 2003 Test Beam Results n (Later, unstructured beam period) n Very high efficiencies achieved u Highest trigger efficiency of 99.9% required low rate (few kHz) n Improved DAQ throughput allowed readout up to 80k full events per spill. Typical “run” is 1 or 2 spills. n Improved scans taken: u Logic scope read out on most data u HV scan u Comparator threshold scan u Pattern requirements scan u Angle scans bb

14. CSC Muon Trigger September 16, 2003 CMS Annual Review 14 Sector Processor Clock Patch Voltage Controlled Crystal Oscillator PLL Patch Low jitter Output Cleans Backplane clock to drive SP logic x2 BackPlane Clock supplies reference to TLK2501 LVDS Repeater Delivers Multiplied Clock to Front FPGAs to Drive TLK2501 clock input VCXO and PLL added to clean synchronous clock

15. CSC Muon Trigger September 16, 2003 CMS Annual Review 15 SP Patch Results ConditionsType of TestTimeErrors Patched CCB Clock, 100m fibers SP  SP loopback PRBS test 5 hours x 3 links0 “ MPC  SP PRBS test (within same TF crate) 24 hours x 3 links0 TTCvx with 40.0787 MHz XO Patch MPC  SP PRBS test (within same TF crate) 32 hours x 3 links0 “ MPC  SP PRBS test (peripheral crate to TF crate) with L1A rate @ 100kHz. 14 hours x 3 links0 n Eagerly awaiting QPLL chips from CERN

16. CSC Muon Trigger September 16, 2003 CMS Annual Review 16 Preparation for Sept. 2003 Beam Test CSCs Scintillator Panels HV Supply CCB MPC DDU Dynatem TMB DMB SP CCB SBS TTCvi TTCvx Cosmic ray test stand in Florida System brought to working order (everything now shipped to CERN) TF Crate Periph Crate

17. CSC Muon Trigger September 16, 2003 CMS Annual Review 17 Conclusions n The CSC system is in very good shape: u Chambers being mounted on disks at SX5 u Majority of the chambers already built and tested, including on- chamber electronics u Test beam showed that CSC peripheral crate electronics work very well under “battle conditions” n Of course, much work remains: u We especially need to validate the optical link clocking for MPC-SP data transfer u Production starts soon for peripheral crate electronics u Production planning will start soon for Track Finder (MPC, SP, MS) boards