1. Part A Final presentation Dynamic System on Programmable Chip By: Nir Shahar and Amir Kleinhendler Supervisor: Ina Rivkin Spring/Winter 2006

2. Global Project goals Designing A New Experiment for undergraduate students at the High Speed Digital Systems Laboratory Based on a Dynamic System (using SOPC platform).Designing A New Experiment for undergraduate students at the High Speed Digital Systems Laboratory Based on a Dynamic System (using SOPC platform). Dynamic Peripheral Designing and Implementation.Dynamic Peripheral Designing and Implementation. Designing A New Experiment for undergraduate students at the High Speed Digital Systems Laboratory Based on a Dynamic System (using SOPC platform).Designing A New Experiment for undergraduate students at the High Speed Digital Systems Laboratory Based on a Dynamic System (using SOPC platform). Dynamic Peripheral Designing and Implementation.Dynamic Peripheral Designing and Implementation.

3. Implementing a Simple Dynamic Peripheral.Implementing a Simple Dynamic Peripheral. Learning The FPGA Methodology.Learning The FPGA Methodology. – FPGA Logical Structure. – XUP Board, Virtex II pro, PPC. – FPGA Design Flow. – FPGA Design Tools ( EDK, ISE, Chip-Scope). –Implementing a Simple Dynamic Peripheral. Learning VHDL Design Methodology.Learning VHDL Design Methodology. –VHDL for Synthesis. –MODEL-SIM for Simulation. –HDL Design Tool. Dynamic Peripheral Designing and Implementation.Dynamic Peripheral Designing and Implementation. Implementing a Simple Dynamic Peripheral.Implementing a Simple Dynamic Peripheral. Learning The FPGA Methodology.Learning The FPGA Methodology. – FPGA Logical Structure. – XUP Board, Virtex II pro, PPC. – FPGA Design Flow. – FPGA Design Tools ( EDK, ISE, Chip-Scope). –Implementing a Simple Dynamic Peripheral. Learning VHDL Design Methodology.Learning VHDL Design Methodology. –VHDL for Synthesis. –MODEL-SIM for Simulation. –HDL Design Tool. PART A Goals

4. The Dynamic System Concept When we simulate a problem we can dynamically remove or replace a peripheral in-order to fix the simulated problem. Option 1 Option 2 Option 3

5. Status Update We have crossed the final step for the project’s first part.We have crossed the final step for the project’s first part. We Have implemented a dynamic periphery.We Have implemented a dynamic periphery. The knowledge we have acquired will be used for the second part of our project.The knowledge we have acquired will be used for the second part of our project. The periphery we have implemented here will demonstrate several problems students will encounter during the experiment.The periphery we have implemented here will demonstrate several problems students will encounter during the experiment. We have crossed the final step for the project’s first part.We have crossed the final step for the project’s first part. We Have implemented a dynamic periphery.We Have implemented a dynamic periphery. The knowledge we have acquired will be used for the second part of our project.The knowledge we have acquired will be used for the second part of our project. The periphery we have implemented here will demonstrate several problems students will encounter during the experiment.The periphery we have implemented here will demonstrate several problems students will encounter during the experiment.

6. System Creation Flow 3 bit FA We planned the block diagram of the complete system.We planned the block diagram of the complete system. We implemented the VHDL code.We implemented the VHDL code. Ran Model Sim simulations for the design (for logic validation).Ran Model Sim simulations for the design (for logic validation). We created a new user periphery with the new logic block (in EDK and ISE).We created a new user periphery with the new logic block (in EDK and ISE). Wrote the C code for the periphery usage.Wrote the C code for the periphery usage. We inserted a ChipScope probe into the design (this part was the most problematic part of the project).We inserted a ChipScope probe into the design (this part was the most problematic part of the project). We validated the functionality of the dynamic FA of the FPGA with the ChipScope.We validated the functionality of the dynamic FA of the FPGA with the ChipScope. We planned the block diagram of the complete system.We planned the block diagram of the complete system. We implemented the VHDL code.We implemented the VHDL code. Ran Model Sim simulations for the design (for logic validation).Ran Model Sim simulations for the design (for logic validation). We created a new user periphery with the new logic block (in EDK and ISE).We created a new user periphery with the new logic block (in EDK and ISE). Wrote the C code for the periphery usage.Wrote the C code for the periphery usage. We inserted a ChipScope probe into the design (this part was the most problematic part of the project).We inserted a ChipScope probe into the design (this part was the most problematic part of the project). We validated the functionality of the dynamic FA of the FPGA with the ChipScope.We validated the functionality of the dynamic FA of the FPGA with the ChipScope.

7. Periphery Top Overview The block diagram of the complete system.

8. We implemented the VHDL code.

9. Created a new user periphery with the new logic block (in EDK and ISE). In this stage we use several VHDL files to implement a design. In the Xilinx environment implementing user logic with several HDL files was challenging.In this stage we use several VHDL files to implement a design. In the Xilinx environment implementing user logic with several HDL files was challenging. We’ve done it by using the PAO file and importing libs.We’ve done it by using the PAO file and importing libs. In this stage we use several VHDL files to implement a design. In the Xilinx environment implementing user logic with several HDL files was challenging.In this stage we use several VHDL files to implement a design. In the Xilinx environment implementing user logic with several HDL files was challenging. We’ve done it by using the PAO file and importing libs.We’ve done it by using the PAO file and importing libs.

10. C code for the periphery usage. We wrote the C code using the Xilinx special commands.We wrote the C code using the Xilinx special commands. For example: XGpio_Initialize(&GpioDipSwitch,XPAR_DIPSWS_4BIT_DEVICE_ID); // set the GpioDipSwitch valueXGpio_Initialize(&GpioDipSwitch,XPAR_DIPSWS_4BIT_DEVICE_ID); // set the GpioDipSwitch value XGpio_SetDataDirection(&GpioDipSwitch, 1, 0x1);// set the GpioDipSwitch as an inputXGpio_SetDataDirection(&GpioDipSwitch, 1, 0x1);// set the GpioDipSwitch as an input FA_mWriteSlaveReg0(XPAR_FA_0_BASEADDR, Temp); //writing data to the unitFA_mWriteSlaveReg0(XPAR_FA_0_BASEADDR, Temp); //writing data to the unit Fa_stat=FA_mReadSlaveReg0(XPAR_FA_0_BASEADDR); //reading data from the unitFa_stat=FA_mReadSlaveReg0(XPAR_FA_0_BASEADDR); //reading data from the unit XGpio_DiscreteWrite(&GpioOutput, 1, dip_stat); //writing to the ledsXGpio_DiscreteWrite(&GpioOutput, 1, dip_stat); //writing to the leds We wrote the C code using the Xilinx special commands.We wrote the C code using the Xilinx special commands. For example: XGpio_Initialize(&GpioDipSwitch,XPAR_DIPSWS_4BIT_DEVICE_ID); // set the GpioDipSwitch valueXGpio_Initialize(&GpioDipSwitch,XPAR_DIPSWS_4BIT_DEVICE_ID); // set the GpioDipSwitch value XGpio_SetDataDirection(&GpioDipSwitch, 1, 0x1);// set the GpioDipSwitch as an inputXGpio_SetDataDirection(&GpioDipSwitch, 1, 0x1);// set the GpioDipSwitch as an input FA_mWriteSlaveReg0(XPAR_FA_0_BASEADDR, Temp); //writing data to the unitFA_mWriteSlaveReg0(XPAR_FA_0_BASEADDR, Temp); //writing data to the unit Fa_stat=FA_mReadSlaveReg0(XPAR_FA_0_BASEADDR); //reading data from the unitFa_stat=FA_mReadSlaveReg0(XPAR_FA_0_BASEADDR); //reading data from the unit XGpio_DiscreteWrite(&GpioOutput, 1, dip_stat); //writing to the ledsXGpio_DiscreteWrite(&GpioOutput, 1, dip_stat); //writing to the leds

11. Inserted a ChipScope probe into the design. Problems : RTL optimization problem. When we synthesized our design with EDK, the ISE tool automatically ran its optimizations, and “optimized away” some of our signals, for efficiency. This phenomena was very problematic on our behalf because we wanted students to be able to see all the design signals. Signals naming problem. After the synthesis stage, some of our original signals received different names, as a part of the synthesis process. It was very difficult to distinguish which were the relevant signals. Problems : RTL optimization problem. When we synthesized our design with EDK, the ISE tool automatically ran its optimizations, and “optimized away” some of our signals, for efficiency. This phenomena was very problematic on our behalf because we wanted students to be able to see all the design signals. Signals naming problem. After the synthesis stage, some of our original signals received different names, as a part of the synthesis process. It was very difficult to distinguish which were the relevant signals.

12. Inserted a ChipScope probe into the design Signals naming problem. ( example )

13. Solution for the post synthesis naming/optimizing problem There were several stages for the solution :There were several stages for the solution : –First we synthesized our periphery in an independent way using ISE. –We learned which libraries are needed in order for us to be able to “dive into” modules in our design. –We found a method of synthesis which preserves the signal names. –We then transferred this knowledge to the EDK environment, and found a method of synthesizing our design with command line instructions for the ISE. –Finally the synthesized peripheries kept their original names and we are now able to monitor all signals of our design. –The signals were also not optimized away There were several stages for the solution :There were several stages for the solution : –First we synthesized our periphery in an independent way using ISE. –We learned which libraries are needed in order for us to be able to “dive into” modules in our design. –We found a method of synthesis which preserves the signal names. –We then transferred this knowledge to the EDK environment, and found a method of synthesizing our design with command line instructions for the ISE. –Finally the synthesized peripheries kept their original names and we are now able to monitor all signals of our design. –The signals were also not optimized away

16. Dynamic validation using the chip scope We picked a collection of signals which are crucial for the observations the students are to make at the experiment.We picked a collection of signals which are crucial for the observations the students are to make at the experiment.

17. Designing The New Dynamic System Experiment.Designing The New Dynamic System Experiment. Building The Experiment Files ( EDK ).Building The Experiment Files ( EDK ). Simulating The Complete Experiment.Simulating The Complete Experiment. Building an Experiment Folio.Building an Experiment Folio. –Pre-experiment learning kit ( includes preparation questions ). –Preparing an experiment booklet. –Preparing a station startup script. Designing The New Dynamic System Experiment.Designing The New Dynamic System Experiment. Building The Experiment Files ( EDK ).Building The Experiment Files ( EDK ). Simulating The Complete Experiment.Simulating The Complete Experiment. Building an Experiment Folio.Building an Experiment Folio. –Pre-experiment learning kit ( includes preparation questions ). –Preparing an experiment booklet. –Preparing a station startup script. PART B: Goals

18. Our plan for the second part of the project is to implement several different peripheries like the one we implemented here. Each periphery will have several different problems.Our plan for the second part of the project is to implement several different peripheries like the one we implemented here. Each periphery will have several different problems. The students will have to detect the problems with the chip scope and fix them by selecting a different configuration for the periphery.The students will have to detect the problems with the chip scope and fix them by selecting a different configuration for the periphery. Our plan for the second part of the project is to implement several different peripheries like the one we implemented here. Each periphery will have several different problems.Our plan for the second part of the project is to implement several different peripheries like the one we implemented here. Each periphery will have several different problems. The students will have to detect the problems with the chip scope and fix them by selecting a different configuration for the periphery.The students will have to detect the problems with the chip scope and fix them by selecting a different configuration for the periphery. PART B: The Experiment

19. Several Ideas for Peripheries A Led lighting design.A Led lighting design. Full adder.Full adder. 4 bit counter.4 bit counter. Stop light designStop light design Etc…(more are optional)Etc…(more are optional) In each periphery we will plant several hardware and software problems. Which will be implemented similar to the way we have implemented them with our FA.In each periphery we will plant several hardware and software problems. Which will be implemented similar to the way we have implemented them with our FA. A Led lighting design.A Led lighting design. Full adder.Full adder. 4 bit counter.4 bit counter. Stop light designStop light design Etc…(more are optional)Etc…(more are optional) In each periphery we will plant several hardware and software problems. Which will be implemented similar to the way we have implemented them with our FA.In each periphery we will plant several hardware and software problems. Which will be implemented similar to the way we have implemented them with our FA.

20. QUESTIONSQUESTIONS

21. GOOD VERSION BACK

22. LOGIC CHANGE BACK

23. CARRY PROBLEM BACK

24. 3 BIT ADDER BACK

25. LOGIC PROBLEM BACK

26. REVESED FF PROBLEM BACK

27. FULL ADDER GOOD BACK

28. FULL ADDER CARRY BACK

29. REVERSED FF BACK

30. FA LOGIC PROBLEM BACK

31. REVERSED FF PROBLEM BACK

32. CARRY PROBLEM BACK