1. Combined Input Output Queuing Switch Simulator The Laboratory of Computer Communication and Networking

2. Team members Developed by: Nir Zepkowitzszefko@t2 Ari Shotlandshota@t2 Amir Nahirsamnahir@t2 Instructor: Dr. Adi Rosen adiro@cs Supervisor: Mr. Guy Sela guysela@tx

3. Project Goal To determine how the memory (buffer space) of a CIOQ switch should be partitioned between the output ports and the input ports, and how the performance of the switch is affected by this division.

4. Project sub - goals Provide an easily configurable switch simulator to allow user to compare switch behavior upon various parameters of both switch and network traffic.Provide an easily configurable switch simulator to allow user to compare switch behavior upon various parameters of both switch and network traffic. Provide a tool for generation of network traffic.Provide a tool for generation of network traffic.

5. Background The increasing speed of communication lines poses technological challenges on the design of network switches. In a nutshell, the problem is that it is hard to build switches with internal speed which is much higher than the speed of current communication lines.The increasing speed of communication lines poses technological challenges on the design of network switches. In a nutshell, the problem is that it is hard to build switches with internal speed which is much higher than the speed of current communication lines.

6. Background Combined Input Output Queued (CIOQ) switches are switches that have buffers both at the input ports and at the output ports. Packets arriving on input ports are first stored in buffers at their input port. They are later transferred to buffers at the output ports, and from there transmitted on the output lines. Typically, the internal speed of such switches is some (small) constant times the speed of the communication lines.Combined Input Output Queued (CIOQ) switches are switches that have buffers both at the input ports and at the output ports. Packets arriving on input ports are first stored in buffers at their input port. They are later transferred to buffers at the output ports, and from there transmitted on the output lines. Typically, the internal speed of such switches is some (small) constant times the speed of the communication lines.

7. Project Architecture The project consists of three main modules:The project consists of three main modules: Network Traffic Generator.Network Traffic Generator. Switch Simulator.Switch Simulator. Report Generator.Report Generator.

8. Simulation Flow

9. The Network Traffic Generator A tool for generating network streams.A tool for generating network streams. The Network Traffic Generator can be configured to generate streams representing different traffic scenarios.The Network Traffic Generator can be configured to generate streams representing different traffic scenarios. Packets arrive at each of the input ports at a Poisson rate determined by the user.Packets arrive at each of the input ports at a Poisson rate determined by the user.

10. NTG – Destination Ports Distribution Uniform distribution - Uniformly choose an output port out of all possible ports.Uniform distribution - Uniformly choose an output port out of all possible ports. Single vector distribution - Choose a port according to its ratio within a single vector of size m (the number of output ports).Single vector distribution - Choose a port according to its ratio within a single vector of size m (the number of output ports). Multi vector distribution - Stating a distribution vector for each input port.Multi vector distribution - Stating a distribution vector for each input port.

11. The Switch Simulator The Switch Simulator can be loaded with several configurations.The Switch Simulator can be loaded with several configurations. The Switch Simulator outputs a CSV format file for the report generator.The Switch Simulator outputs a CSV format file for the report generator.

12. Configuring The Switch Simulator A single configuration is supplied for the physical parameters of the switch: number of input, number of output ports and simulation time.A single configuration is supplied for the physical parameters of the switch: number of input, number of output ports and simulation time. The simulator can be loaded with several configurations each describing a switch behavior to simulate.The simulator can be loaded with several configurations each describing a switch behavior to simulate.

13. Configuring a Switch Behavior The following parameters defines a switch: Input Queuing Algorithm: FIFO, VOQ and Shared Memory.Input Queuing Algorithm: FIFO, VOQ and Shared Memory. Fabric Matching Algorithm : Maximum matching, Weighted Matching.Fabric Matching Algorithm : Maximum matching, Weighted Matching. Fabric SpeedUp.Fabric SpeedUp. Memory Size.Memory Size. Input Buffer percentage.Input Buffer percentage.

14. Virtual Output Queuing Buffer Each input buffer is divided into m (the number of output ports) logical buffers, each logical buffer is a FIFO queue. Input port 2 Output port 1 Output port 2 Output port 3 Output port 4 Accessible packets

15. Shared Memory Buffer packets in the shared memory buffer can be accessed randomly in a manner that will serve the matching algorithm in the best way.packets in the shared memory buffer can be accessed randomly in a manner that will serve the matching algorithm in the best way. Input port 2 Output port 1 Output port 2 Output port 3 Output port 4 Accessible packets

16. Maximum Matching Algorithm Matches the maximum number of packets possible. Implemented using Ford-Fulkerson’s max flow algorithm. Super-source Super-target Input ports Output ports

17. Weighted Matching Algorithm Each input buffer is assigned a weight proportionate to its occupancy.Each input buffer is assigned a weight proportionate to its occupancy. Each output buffer is assigned a weight inverse-proportionate to its occupancy.Each output buffer is assigned a weight inverse-proportionate to its occupancy. Each packet is assigned a weight which is the sum of the input port weight and the output port weight.Each packet is assigned a weight which is the sum of the input port weight and the output port weight.

18. Weighted Matching Algorithm The algorithm is greedy: first, it tries to add packets with maximum possible weight. than, it tries to add packets with maximum possible weight – 1. …

19. Simulator Output The Switch Simulator creates a CSV format file with data representing simulation results: A time slot based table holding all raw data of the simulation process including the state of all buffers (input and output), the total number of packets that have entered the switch, the total number of packets that were lost until this time slot and the number of packets transferred over the fabric.A time slot based table holding all raw data of the simulation process including the state of all buffers (input and output), the total number of packets that have entered the switch, the total number of packets that were lost until this time slot and the number of packets transferred over the fabric. A summary of packet loss percentage for each configuration.A summary of packet loss percentage for each configuration.

20. Simulator Output Tables holding data of all possible comparisons between simulation results of the different configurations. Each table consists of two or more configurations that differ on a single parameter.Tables holding data of all possible comparisons between simulation results of the different configurations. Each table consists of two or more configurations that differ on a single parameter.

21. Report Generator All output is written in a CSV format so further analysis and processing can be done with MS Excel. Exemplary Results

22. Extending The Simulator The simulator was designed to be extendible.The simulator was designed to be extendible. The Switch Simulator module consists of three main sub – modules:The Switch Simulator module consists of three main sub – modules: SwitchSwitch BuffersBuffers Matching algorithmsMatching algorithms

23. Extending The Simulator Buffer Interfaces Matching Algorithm Interface Architecture Of The Switch Simulator Sub Modules Switch Sub - Module

24. Extending The Simulator You can extend the type of buffers and modules supported by the switch by designing your own buffers and matching algorithms objects and adding them to appropriate Create() global methods. Buffer Interface CreateBuffer() BUFFER_TYPE + Parameters Algorithm Interface CreateAlgorithm() ALG_TYPE + Parameters Buffer Object Algorithm Object

25. Q & A Head Of Line Case Study

26. Exemplary Results

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