1. 22 nd IEEE VLSI Test Symposium (VTS 2004) Napa Valley, CA

2. Welcome Message André Ivanov General Chair

3. Keynote Address Ulrich Seif Senior VP & Chief Information Officer National Semiconductor

4. Program Introduction Irith Pomeranz Program Chair

5. The VTS Contents Technical Paper Sessions Technical Paper Sessions Special Sessions Special Sessions Innovative Practices Track Innovative Practices Track

6. Technical Paper Selection Expert reviewers recommended by the program committee Expert reviewers recommended by the program committee At least three reviews for every submitted paper At least three reviews for every submitted paper Multi-site program committee meeting (Fremont, CA; Princeton, NJ; Stuttgart, Germany) Multi-site program committee meeting (Fremont, CA; Princeton, NJ; Stuttgart, Germany)

7. Thanks 38 program committee members 38 program committee members 13 organizing committee member 13 organizing committee member 7 steering committee members 7 steering committee members 237 reviewers 237 reviewers 747 reviews 747 reviews

9. Special Thanks Program committee members Program committee members Hans Manhaeve Hans Manhaeve Subhasish Mitra Subhasish Mitra Sudhakar Reddy Sudhakar Reddy Organizing committee members Organizing committee members Pritha Roy Pritha Roy Burnie West Burnie West

10. Technical Paper Sessions Test Data Compression & Low-Speed ATE Memory Testing I,IIIssues in Reliability Logic BIST MEMs Testing and FPGA Testing Wireless and System Testing Current Based Testing SoC Testing Pattern Debug, Yield Analysis and FPGA Testing Low-Voltage and Thermal Testing Defect-Oriented Testing Defect Analysis and Fault Simulation DelayTesting Analog Testing I,II,III

11. IP Track Silicon Debug and Diagnosis Silicon Debug and Diagnosis Test and Repair of Large Memory Systems Test and Repair of Large Memory Systems Test Compression Test Compression Latest Results in Wireless Test Latest Results in Wireless Test SoC Test Practice in Japan SoC Test Practice in Japan Leading Edge Practices for Yield Enhancement Leading Edge Practices for Yield Enhancement Optimizing Manufacturing Process Optimizing Manufacturing Process

12. Special Sessions Embedded Tutorials: Embedded Tutorials: Challenges in Embedded Memory Test and Diagnosis Challenges in Embedded Memory Test and Diagnosis Advances in Wafer Probe Test Advances in Wafer Probe Test Reliability and Dependability Reliability and Dependability Design for Yield Design for Yield Design for Manufacturability Design for Manufacturability Hot Topics: Hot Topics: Testing of Nanocircuits with High Defect Densities Testing of Nanocircuits with High Defect Densities Advances in 3D Packaging Advances in 3D Packaging Software Based Embedded Test Software Based Embedded Test Panels: Panels: Elevator Talks Elevator Talks Process Variation: How Severe is the Problem of D&T? Process Variation: How Severe is the Problem of D&T? Defect-Based Testing and Burn-In: A Test Solution for Scaled Technology? Defect-Based Testing and Burn-In: A Test Solution for Scaled Technology?

13. Invited Keynote Kamalesh Ruparel Senior Director Cisco Systems

14. TTTC Ned Kornfield Memorial Presentation Yervant Zorian TTTC Senior Past Chair

15. Awards

16. TTTC Naveena Nagi Award

17. TTTC Most Successful Technical Meeting Award

18. TTTC Most Populous Technical Meeting Award

19. VTS 2003 Best Paper Award

20. VTS 2003 Best Panel Award

21. VTS 2003 Best IP Session Award