1. Sequential Logic Design
Truth Table
Sequential Logic Design Q3 Q2 Q1 D3 D2 D1 1
State Diagram (State transition table): A Case Study: design an 3-bit counter that only counts 1,3,5,7 using D FF
000
110
100
010
001
111
101
011
The Karnaugh map for D2 is:
For unused states, usually reset to 000, or 111 Q1 1
Q3Q2 00 01 11 10
Red supercell: Q1’
Green supercell: Q2’

2. Example 2: Modulo-4 binary up-down count
Counting up or down from 0-3
input 1, counts up
input 0, counts down
Choose RS FF, needs two

3. Implementation of Modulo-4 counter