1. FSMs 1 Sequential logic implementation  Sequential circuits  primitive sequential elements  combinational logic  Models for representing sequential circuits  finite-state machines (Moore and Mealy)  representation of memory (states)  changes in state (transitions)  Basic sequential circuits  shift registers  counters  Design procedure  state diagrams  state transition table  next state functions

2. FSMs 2 Any sequential system can be represented with a state diagram  Shift register  input value shown on transition arcs  output values shown within state node 100 110 111 011 101010 000 001 0 1 1 1 1 1 1 1 0 0 0 0 0 1 0 0 DQDQDQ IN OUT1OUT2OUT3 CLK

3. FSMs 3 State machine model  Values stored in registers are the state of the circuit  Combinational logic computes:  next state  outputs  function of current state and inputs (Mealy machine)  function of current state only (Moore machine) Inputs Outputs Next State Current State output logic next state logic

4. FSMs 4 State Machine Model  States: S1, S2,..., Sk  Inputs: I1, I2,..., Im  Outputs: O1, O2,..., On  Transition function: Fs(Si, Ij)  Output function: Fo(Si) or Fo(Si, Ij) Inputs Outputs Next State Current State output logic next state logic

5. FSMs 5 How do we turn a state diagram into logic?  e.g. counter  flip-flops to hold state  logic to compute next state  clock signal controls when flip-flop memory can change  wait just long enough for combinational logic to compute new value

6. FSMs 6 FSM design procedure  Describe FSM behavior, e.g. state diagram  Inputs and Outputs  States (symbolic)  State transitions  State diagram to state transition table, i.e. truth table  Inputs: inputs and current state  Outputs: outputs and next state  State encoding  decide on representation of states  lots of choices  Implementation  flip-flop for each state bit  synthesize combinational logic from encoded state table

7. FSMs 7 Present StateNext State CBAC+B+A+ 000xxx 001xxx 010101 011110 100010 101011 110100 111xxx note the don't care conditions that arise from the unused state codes Synthesis Example  Implement simple count sequence: 000, 010, 011, 101, 110  Derive the state transition table from the state transition diagram 101 010100 110 011

8. FSMs 8 C B A X110X1X0X110X1X0 C+C+ C B A X001X1X1X001X1X1 B+B+ C B A X100X0X1X100X0X1 A+A+ C + = B B + = A + B’ C A + = A’ C’ + AC Don’t cares in FSMs (cont’d)  Synthesize logic for next state functions derive input equations for flip- flops

9. FSMs 9 Self-starting FSMs  Deriving state transition table from don't care assignment C B A 0110011001100110 C+C+ C B A 1001111110011111 B+B+ C B A 1100001111000011 A+A+ Present StateNext State CBAC+B+A+ 000011 001010 010101 011110 100010 101011 110100 11111x

10. FSMs 10 implementation on previous slide Self-starting FSMs  Start-up states  at power-up, FSM may be in an used or invalid state  design must guarantee that it (eventually) enters a valid state  Self-starting solution  design FSM so that all the invalid states eventually  transition to a valid state may limit exploitation of don't cares 101 010100 110 011 000 001 111

11. FSMs 11 Mealy vs. Moore Machines  Moore: outputs depend on current state only  Mealy: outputs may depend on current state and current inputs A L’ R’ / TR, F L / TL L’ R / TL, F

12. FSMs 12 D/1 E/1 B/0 A/0 C/0 1 0 0 0 0 1 1 1 1 0 reset currentnext resetinputstatestateoutput 1––A 00AB0 01AC0 00BB0 01BD0 00CE0 01CC0 00DE1 01DC1 00EB1 01ED1 Specifying outputs for a Moore machine  Output is only function of state  specify in state bubble in state diagram  Example (what does it do?)

13. FSMs 13 currentnext resetinputstatestateoutput 1––A0 00AB0 01AC0 00BB0 01BC1 00CB1 01CC0 B A C 0/1 0/0 1/1 1/0 reset/0 Specifying outputs for a Mealy machine  Output is function of state and inputs  specify output on transition arc between states

14. FSMs 14 state feedback inputs outputsreg combinational logic for next state logic for outputs inputsoutputs state feedback reg combinational logic for next state logic for outputs Comparison of Mealy and Moore machines  Mealy machines tend to have fewer states  different outputs on arcs (i*n) rather than states (n)  Mealy machines react faster to inputs  react in same cycle – don't need to wait for clock  delay to output depends on arrival of input  Moore machines are generally safer to use  outputs change at clock edge (always one cycle later)  in Mealy machines, input change can cause output change as soon as logic is done – a big problem when two machines are interconnected – asynchronous feedback

15. FSMs 15 ABCinCoutS 000 00 00101 01001 01110 10001 10110 11010 11111 P.S.N.S. Isn’t Mealy Always Better?  Example: serial adder - add bits arriving serially on two input wires  Adding 5 serial numbers on 5 separate lines  What is the clock period of this circuit? A B CDE Sum ABAB S ABAB S ABAB S ABAB S A B S Cout Cin combinational logic

16. FSMs 16 Moore Implementation - Pipelined  Example: adding 5 serial numbers  What is the clock period of this circuit? A0 A1 A2 A3 A4 Sum ABAB S ABAB S ABAB S ABAB S A B Cin combinational logic Cout

17. FSMs 17 Example Abstract Verilog FSM – Breshenham’s Algorithm module breshenham (clk, reset, x1, y1, x2, y2, x, y); input clk, reset; input [7:0] x1, y1, x2, y2; output [7:0] x, y; REGISTER t = 0; REGISTER [7:0] x, y; REGSITER [7:0] dx, dy; parameter INIT=0, RUN=1, DONE=2; REGISTER [2:0] state = INIT; COMB [7:0] temp; ALWAYS begin case (state) INIT: begin x <-- x1; y <-- y1; dx <-- x2 – x1; dy = y2 – y1; t <-- 0; state <-- RUN; end RUN: begin temp = t + dy; if (temp = dx) begin y <-- y + 1; t <-- temp – dx; end else begin t <-- temp; end x <-- x + 1; if (x >= x2) state <-- DONE; end DONE: begin... end endmodule

18. FSMs 18 Design Problem – Run-Length Encoder  7-bit input stream  8-bit output stream  high-order bit == 0: Data value  high-order bit == 1: Repeat count of previous data value  Valid bit set when 8-bit output is data or count

19. FSMs 19 RLE Design  Split design into datapath and control  Datapath  Registers for data values, count  Multiplexors  Control  Keep track of what’s happening  clear count, increment count, send data value, send count  Control will be an FSM

20. FSMs 20 Start with Datapath  We need to know what to control  FSM inputs  eq  FSM outputs  clr, inc, valid, cnt,

21. FSMs 21 FSM Controller

22. FSMs 22 Verilog For State Machines  State machine has two parts  State register  Combinational Logic  Next state function  Output function  Each in a different always block inputs Moore outputs Mealy outputs next state current state combinational logic

23. FSMs 23 Implementing an FSM  1. Perform state assignment  different assignments may give very different results  no really good heuristics  using an extra bit or two for state works well  FPGAs often us a 1-hot encoding  2. Convert state diagram to state table  equivalent representation  mechanical  3. State table gives truth table for next state and output functions  synthesize into logic circuit  e.g. 2-level logic implementation

24. FSMs 24 RLE State Table  reset is implicit – resets state register eqstatenext stateclrincvalidcnttag -START1START2xx0x - SENDINGxx0x 0 xx10 1 COUNTING1x10 0 SENDINGxx11 1COUNTING 010x

25. FSMs 25 RLE State Table  minimal binary encoding  there are 6 output functions eqstatenext stateclrincvalidcnttag -0001xx0x - 10xx0x 0 xx10 1 111x10 0 10xx11 111 010x

26. FSMs 26 Logic Synthesis Q1state 00011110 eq00111 10111 Q0state 00011110 eq01000 11011 clrstate 00011110 eq0XXXX 1XX01 validstate 00011110 eq00011 10001 incstate 00011110 eq0XXXX 1XX1X cnttagstate 00011110 eq0XXX0 1XX10 Q1 = Q1 + Q0 Q0 = Q1’ Q0’ + eq Q1 clr = Q0’ inc = 1 valid = eq’ Q1 + Q1 Q0’ = Q1 (eq’ + Q0’) cnttag = Q0 6 gates

27. FSMs 27 RLE State Table  1-hot encoding  there are 8 output functions eqstatenext stateclrincvalidcnttag -00010010xx0x - 0100xx0x 0 xx10 1 10001x10 0 0100xx11 11000 010x

28. FSMs 28 1-Hot Logic Functions  Synthesize directly from table Q0 = reset Q1 = Q0 Q2 = Q1 + eq’ (Q2 + Q3) Q3 = eq (Q2 + Q3) inc = 1 clr = Q2 valid = Q2 + eq’ Q3 cnttag = Q3  Same cost as minimal encoding (6 gates)