1. August 12, 2005Uppalapati et al.: VDAT'051 Glitch-Free Design of Low Power ASICs Using Customized Resistive Feedthrough Cells 9th VLSI Design & Test Symposium – VDAT ’05 Bangalore, August 10-13, 2005 Siri Uppalapati GDA Tech., Inc. San Jose, CA 95131, USA siri@gdatech.com Michael L. Bushnell Rutgers University Piscataway, NJ 08854, USA bushnell@caip.rutgers.edu Vishwani D. Agrawal Auburn University Auburn, AL 36849, USA vagrawal@eng.auburn.edu

2. August 12, 2005Uppalapati et al.: VDAT'052 Motivation Application Specific Integrated Circuit (ASIC) chips employ standard cell design style. Dynamic power consumed by glitches in a CMOS circuit, though significant, can be reduced or eliminated by design. Existing glitch reduction techniques demand customized gate design, not suitable for a standard cell ASIC.

3. August 12, 2005Uppalapati et al.: VDAT'053 Power Dissipation in CMOS Logic (0.25µ) %75%5%20 P total (0→1) = C L V DD 2 + t sc V DD I peak + V DD I leakage CLCL

4. August 12, 2005Uppalapati et al.: VDAT'054 Prior Work: Hazard Filtering Glitch is suppressed when the inertial delay of gate exceeds the differential input delay. 1 or 3 2 Filtering Effect of a gate Reference: V. D. Agrawal, “Low Power Design by Hazard Filtering”, VLSI Design 1997. or 2 2

5. August 12, 2005Uppalapati et al.: VDAT'055 Prior Work: A Reduced Constraint Set LP Model for Glitch Removal Satisfy glitch suppression condition at all gates: Differential path delay at gate input < inertial delay Use a linear program (LP) to find delays –Path enumeration avoided –Reduced (linear) size of LP allows scalability Design gates with specified delays 40-60% dynamic power savings in custom design Procedure is not suitable for pre-designed cell libraries Reference: T. Raja, V. D. Agrawal and M. L. Bushnell, “Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program,” VLSI Design 2003.

6. August 12, 2005Uppalapati et al.: VDAT'056 Prior Work: ASIC J. M. Masgonty, S. Cserveny, C. Arm and P. D. Pfister, “Low-Power Low-Voltage Standard Cell Libraries with a Limited Number of Cells”, PATMOS ’01 –Transistor sizing results in 20 - 25% savings in power –Power optimized by minimizing parasitic capacitances –No glitch reduction attempted Y. Zhang, X. Hu and D. Z. Chen, “Cell Selection from Technology Libraries for Minimizing Power”, DAC ’01 –Mixed Integer Linear Program (MILP) to select from different realizations of cells such that power consumption is minimized without violating delay constraints –Sum of dynamic and leakage power is minimized –Library contains cells of varying sizes, supply voltages, and threshold voltages –Achieved 79% power saving on an average –No glitch reduction attempted.

7. August 12, 2005Uppalapati et al.: VDAT'057 New Glitch Removing Solution Balanced the differential delays at cell inputs: –Using delay elements called Resistive Feedthrough cells Automated the delay element –Generation –Insertion into the circuit

8. August 12, 2005Uppalapati et al.: VDAT'058 Comparison of Delay Elements Delay element Average delay (ns) Delay/ Power Delay /Area I0.280.22.03 II0.594.430.05 III0.725.540.11 IV0.631.050.16 II. n diffusion capacitor III. Polysilicon resistor IV. Transmission gate I. Inverter pair Resistor shows –Maximum delay –Minimum power and area per unit delay –Hence, best delay element Resistive feed through cell –A fictitious buffer at logic level

9. August 12, 2005Uppalapati et al.: VDAT'059 Resistive Feedthrough Cell A parameterized cell Physical design is simple – easily automated No routing layers(M2 to M5) used – not an obstruction to the router R □ *(length of poly) Width of poly R = S. Uppalapati, “Low Power Design of Standard Cell Digital VLSI Circuits,” Master’s Thesis, Rutgers University, Dept. of ECE, Piscataway, NJ, Oct. 2004.

10. August 12, 2005Uppalapati et al.: VDAT'0510 RC Delay Model C L varies during transition ( model not perfectly linear) Spectre simulation data stored as a 3D lookup table Average of signal rise and fall delays Linear interpolation used T PLH + T PHL 2 T P = Vin R CLCL Vout CLCL R TPTP

11. August 12, 2005Uppalapati et al.: VDAT'0511 Design Optimization Flow Design Entry Tech. Mapping Layout Remove Glitches Find delays from LP Find resistor values from lookup table Generate feed through cells and modify netlist

12. August 12, 2005Uppalapati et al.: VDAT'0512 Results Circuit New Standard Cell Based Design Power saved (%) in custom design Raja et al. Area overhead (%) Power saved (%) 4 bit ALU29.523.7N/A c432114.050.035.0 C49986.032.029.0 C88098.043.044.0 C135522.068.356.0 C267014.030.031.0 S. Uppalapati, “Low Power Design of Standard Cell Digital VLSI Circuits,” Master’s Thesis, Rutgers University, Dept. of ECE, Piscataway, NJ, Oct. 2004.

13. August 12, 2005Uppalapati et al.: VDAT'0513 Glitch Elimination on net86 in 4bit ALU Source: Post layout simulation in SPECTRE

14. August 12, 2005Uppalapati et al.: VDAT'0514 Layouts of c880 Original layout of c880Optimized layout of c880 Power saving = 43% Area increase= 98%

15. August 12, 2005Uppalapati et al.: VDAT'0515 Conclusion Successfully devised a glitch removal method for the standard cell based design style Does not require redesign of the library cells Does not increase the critical path delay Modified design flow maintains the benefits of ASIC On an average Dynamic power saving: 41% Area overhead: 60% Possible ways to reduce area overhead Cell replacements from existing library On-the-fly-cell design Adjust routing delays for glitch suppression