1. Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR Topics n Multipliers.

2. Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR Elementary school algorithm 0 1 1 0multiplicand x 1 0 0 1multiplier 0 1 1 0 + 0 0 0 0 0 0 1 1 0 + 0 0 0 0 0 0 0 1 1 0 + 0 1 1 0 0 1 1 0 1 1 0 partial product

3. Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR

4. Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR Array multiplier n Array multiplier is an efficient layout of a combinational multiplier. n Array multipliers may be pipelined to decrease clock period at the expense of latency.

5. Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR Array multiplier organization 0 1 1 0 x 1 0 0 1 0 1 1 0 + 0 0 0 0 0 0 1 1 0 + 0 0 0 0 0 0 0 1 1 0 + 0 1 1 0 0 1 1 0 1 1 0 product skew array for rectangular layout multiplicand multiplier

6. Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR Unsigned array multiplier + x0y0x1y0x2y0 xny0 0 x0y1 + x1y1 0 + x0y2 + x1y2 + 0 + P(2n-1) P(2n-2) P0

7. Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR Baugh-Wooley multiplier n Algorithm for two’s - complement multiplication. n Adjusts partial products to maximize regularity of multiplication array. n Moves partial products with negative signs to the last steps; also adds negation of partial products rather than subtracts.

8. Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR

9. Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR Booth multiplier n Encoding scheme to reduce number of stages in multiplication. n Performs two bits of multiplication at once - requires half the stages. n Each stage is slightly more complex than simple multiplier, but adder/subtracter is almost as small/fast as adder.

10. Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR Booth encoding n Two’s-complement form of multiplier: –y = -2 n y n + 2 n-1 y n-1 + 2 n-2 y n-2 +... n Rewrite using 2 a = 2 a+1 - 2 a : –y = 2 n (y n-1 -y n ) + 2 n-1 (y n-2 -y n-1 ) + 2 n-2 (y n-3 -y n-2 ) +... n Consider first two terms: by looking at three bits of y, we can determine whether to add x, 2x to partial product.

11. Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR Booth actions y i y i-1 y i-2 increment 0 0 00 0 0 1x 0 1 0x 0 1 12x 1 0 0-2x 1 0 1-x 1 1 0-x 1 1 10

12. Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR Booth example n x = 011001 (25 10 ), y = 101110 (-18 10 ). y 1 y 0 y -1 = 100, P 1 = P 0 - (10  011001) = 11111001110. y 3 y 2 y 1 = 111, P 2 = P 1  0 = 11111001110. n y 5 y 4 y 3 = 101, P 3 = P 2 - 0110010000 = 11000111110.

13. Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR Booth structure

14. Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR Wallace tree n Reduces depth of adder chain. n Built from carry-save adders: –three inputs a, b, c –produces two outputs y, z such that y + z = a + b + c n Carry-save equations: –y i = parity(a i,b i,c i ) –z i = majority(a i,b i,c i )

15. Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR Wallace tree structure

16. Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR Wallace tree operation n At each stage, i numbers are combined to form ceil(2i/3) sums. n Final adder completes the summation. n Wiring is more complex. n Can build a Booth-encoded Wallace tree multiplier.

17. Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR Serial-parallel multiplier n Used in serial-arithmetic operations. n Multiplicand can be held in place by register. n Multiplier is shfited into array.

18. Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR Serial-parallel multiplier structure

19. Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR