1. CHAPTER 4 COMPUTER SYSTEM – Von Neumann Model
Topics
Basic components of a computer
Instruction processing
Examples from the LC-3 simulator
Changing the sequence of execution
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2. Basic Components of a Computer System
The basic components are:
Central processing unit (CPU)
Memory
Input devices
Output devices
A clock controls all the operations performed in a computer system.
A computer system is a synchronous machine.
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3. Von Neumann Model of a Computer System
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4. Central Processing Unit (CPU)
The CPU consists of:
Arithmetic logic unit (ALU)
Control unit (CU)
Small set of storage areas, called registers
Arithmetic Logic Unit (ALU)
The ALU is the primary processing unit in a computer.
It performs all the arithmetic and logic operations.
Control Unit (CU)
The CU controls all the operations performed by a computer and determines what operations the program calls for and in what order they need to be carried out.
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5. CPU (Continued) The CPU is responsible for:
The complete processing of information
All the decision-making operations
Word Size of a processor:
Number of bits the processor reads from or writes into the memory in one clock cycle
Number of bits normally processed by ALU in one instruction
Also width of registers
LC-3 is a 16 bit processor
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6. Memory Memory provides the storage space for
the program that is currently being executed
the data that is needed during the execution of the program
The memory unit consists of a number of memory locations of the same width.
The number of bits that can be stored in a memory location corresponds to the memory width.
Each memory location is identified by a unique address.
Memory capacity = Total number of memory locations * memory width
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7. Interface to Memory MAR: Memory Address Register
MDR: Memory Data Register
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8. Block Diagram of a Memory Unit
memory width 1 2 .
MAR bits bits MDR
10-bit memory address bit data
(A9 – A0) (D7 – D0)
1023
For this example, memory capacity = 210 x 8 bits = 1 Kbytes
(The above figure does not show the control signals needed to control the memory read and memory write operations.)
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9. Memory - Basic Operations
LOAD - Read data from a memory location
Write the address of the location into the MAR.
Send a “read” signal to the memory.
Read the data from MDR.
STORE - Write data to a memory location
Write the data to the MDR.
Send a “write” signal to the memory.
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10. Input/Output (I/O) Devices
Input devices transfer information from the outside world into the memory of a computer system.
Examples: Keyboard, disk drives, scanner, mouse
Output devices transfer information from the memory of a computer system into the outside world.
Examples: Printers, display units, plotters, disk drives
Some devices provide both input and output
Examples: disk, network
Driver - Program that controls access to a device
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11. Buses in a Computer System
Buses are the physical link between the various
components within the computer.
The computer employs mainly three types of buses:
Address bus
Data bus
Control bus
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12. Buses in a Computer System (Continued)
Three types of buses in a computer system:
Address bus: Carries the address generated by the CPU to the memory and I/O.
Data bus: Allows the transfer of data between the CPU, memory and I/O.
Control bus: Carries the control signals, generated by the control unit, to the various components in the system in order to ensure proper sequencing of data and instruction movement.
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13. Block Diagram of a Basic Computer Architecture
CPU
Clock
CU ALU Clock Generator
Address Bus p
Data Bus q
Control Bus r
  Main Memory I/O Unit
I/O Bus (represents address, data, & control)
  Keyboard Printer Secondary Memory
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14. The instruction specifies two items:
Opcode: operation to be performed
Operands: data/locations to be used for operation
An instruction is encoded as a sequence of bits. Often,
but not always, instructions have a fixed length, such as
16 or 32 bits.
Instruction Format – The binary representation of an instruction
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15. Instruction (Continued)
Control unit
interprets the instruction
generates sequence of control signals to carry out operation.
A computer’s instructions and their formats is known as
its Instruction Set Architecture (ISA).
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16. Instruction Processing
Fetch instruction from memory
Decode instruction
Evaluate address
Fetch operands from memory
Execute operation
Store result
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17. Instruction Processing: FETCH
Load the instruction from memory into
Instruction Register
Copy contents of PC into MAR
MAR ← PC
Increment PC so that PC points to the next instruction in sequence
PC ← PC + 1
Send “read” control signal to memory
MDR ← Memory [MAR]
Copy contents of MDR into IR
IR ← MDR D EA OP EX S
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18. Example Instruction: LDR Instruction
LDR R2, R3, #6 – Loads (reads) data from memory
into the destination register R2
Memory address: Base register + SEXT (offset)
Memory address = R3 + 6
Load the contents of the memory location [R3 + 6] to R2
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19. Instruction Processing: DECODEF
First identify the opcode
Identify the operands
Example: LDR R2, R3, #6
Opcode: IR[15:12] = 0110
Operands:
Offset: IR[5:0] = #6 (6 decimal; binary)
Base register: IR[8:6] = 011 = R3 D EA OP EX S
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20. Instruction Processing: EVALUATE ADDRESSF
For instructions that require memory access,
compute address used for memory access.
Example: LDR R2, R3, #6
Address = SEXT (offset) + Base Register
MAR ← 6 + R3 D EA OP EX S
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21. Instruction Processing: FETCH OPERANDS
Obtain source operands needed to
perform operation.
Example: LDR R2, R3, #6
Load data from memory (LDR)
MDR ← Memory [MAR] D EA OP EX S
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22. Instruction Processing: EXECUTEF
Perform the operation, using the source
operands.
Example: LDR R2, R3, #6
No operation done in this step D EA OP EX S
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23. Instruction Processing: STORE RESULTF
Write results to destination.
Destination can be a register or
Memory.
Example: LDR R2, R3, #6
Data read from the memory is placed in
destination register.
R2 ← MDR D EA OP EX S
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24. Changing the Sequence of Instructions
In the FETCH phase, we increment PC by 1.
Need special instructions called control instructions to
change the contents of the PC during the Execute
phase.
jumps (unconditional)
Always change the PC
branches (conditional)
PC is changed only if the specified condition is
true
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25. Examples: LC-3 Control Instructions
JMP R2 ; PC ← R2
RET ; PC ← R7
BRzp NEXT ; if the last result was zero or positive then
PC ← address corresponding to NEXT
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26. Instruction Processing Summary
Three basic kinds of instructions:
Arithmetic/logic instructions (ADD, AND, …)
Data transfer instructions (LD, ST, …)
Control instructions (JMP, BRnz, …)
Six basic phases of instruction processing:
F  D  EA  OP  EX  S
Not all phases are needed by every instruction
Phases may take variable number of machine cycles
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27. Example Instruction: LDR Instruction
LDR R2, R3, #6 ; R2 ← mem [R3 + 6]
Opcode: IR[15:12] = 0110
Operands:
Base register: R3 given by IR[8:6] Offset: 6 given by IR[5:0]
Destination: R2 given by IR[11:9]
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28. Instruction Processing: LDR R2, R3, #6
Fetch
MAR ← PC
PC ← PC + 1
MDR ← Memory [MAR]
IR ← MDR
Decode
Identify the opcode
Identify the operands
Execute
MAR ← 6 + R3
R2 ← MDR
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29. Example Instruction: ADD Instruction
ADD R6, R2, R6 ; R6 ← R2 + R6
Opcode: IR[15:12] = 0001
Operands:
Source1: R2 given by IR[8:6] Source2: R6 given by IR[2:0]
Destination: R6 given by IR[11:9]
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30. Instruction Processing: ADD R6, R2, R6
Fetch
MAR ← PC
PC ← PC + 1
MDR ← Memory [MAR]
IR ← MDR
Decode
Identify the opcode
Identify the operands
Execute
R6 ← R2 + R6
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31. Example Instruction: JMP Instruction
JMP R3 ; PC ← R3
Opcode: IR[15:12] = 0001
Operand: Base register R3 given by IR[8:6]
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32. Instruction Processing: JMP R3
Fetch
MAR ← PC
PC ← PC + 1
MDR ← Memory [MAR]
IR ← MDR
Decode
Identify the opcode
Identify the operand
Execute
PC ← R3
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