1. 1 HW/SW Partitioning Embedded Systems Design

2. 2 Hardware/Software Codesign “Exploration of the system design space formed by combinations of hardware software component” [Kaplan, Sarrafzadeh, Kastner 2003]

3. 3 Hardware/Software Partitioning Division of system specification into hardware and software components –What are the criteria we need to perform partitioning?

4. 4 Partitioning CAD optimization problem –occurs at every level of abstraction grouping of related modules to satisfy constraints optimize design criteria –examples put highly connected gates in the same partition

5. 5 Partitioning Hierarchical model –standard cells –macro cells (logic) –blocks (architecture)

6. 6 Partitioning K-way partitioning problem Evaluation is done through estimation function –take a partition (or cluster) P and returns a set of evaluated design parameters, DP DP represents properties of the circuit such as area, power, throughput, latency, etc. –whether the constraints are met, and the system is optimized

7. 7 So what then is HW/SW partitioning Original goal: to find a partitioning configuration that satisfies the required performance (constraints) with minimum amount of hardware area (optimization) Other goals –fixed hardware size (constraint) -> maximum execution performance (optimization) –fixed hardware size (constraint) -> minimum energy consumption –realtime requirement (constraint) -> minimum hardware usage (optimization)

8. 8 HW/SW Partitioning NP Complete –exploration of a designed space that is exponential in size Must be done early in the design cycle –accurate estimation function is needed

9. 9 HW/SW Partitioning Early system –task level partitioning (coarse grain) –extracted software portions as targets for hardware realization based on three criteria impact of partition on the overall execution time execution time difference between hardware and software implementation of the same task total cost of hardware

10. 10 HW/SW Partitioning Heuristic search approach (Gupta et al.) –looking for satisfactory performance with minimal cost –greedy base algorithm –operation level –initial condition -> all hardware systems can satisfy the performance requirement

11. 11 HW/SW Partitioning Heuristic search approach –move operation out to software based on communication overhead –movements were not taken if it does not improve the cost of the system often get stuck in local minimum -> sub-optimal partitioning result in solutions with expensive hardware cost

12. 12 HW/SW Partitioning Hill climbing (Ernst et al.) –Start with an initial partitioning that was improved in sub-sequent iterations –use simulated annealing to avoid local minimum accept changes that increase the cost of a design, in hopes of achieving a more optimal final design Petri Net (Vahid et al.)

13. 13 Software Side Compile code to existing but not complete environment –Stub code can be used to simulate hardware interaction Function calls that simulate non existing hardware –Calls to memory mapped I/O registers –Also work well with evolution boards Supply by manufacturers Incremental code written in anticipation for new hardware components –Based on known hardware specification

14. 14 Hardware SoC Mapping of complex algorithms into hardware is now possible –½ reduction in physical size = 4 times the amount of gates 0.35 micron to 0.18 micron Increasing wafer size Silicon compilation –VHDL or Verilog All modern processors use this approach IP from third party vendors –Fab-less vendors (Advanced RISC Machines)

15. 15 Dealing with Defects Software bugs are tolerable and less costly to fix. Hardware bugs on the other hand… –Can cost hundreds of thousands in nonrecoverable cost (NRE) –Months of delay Many start-ups went down because of this reason –Non-performing hardware Repartitioning decision in the last minute

16. 16 HW/SW Co-design and Co- verification Silicon compilation creates a single software database –One for describing hardware fabrication –One for controlling the hardware itself Specification Software Development Hardware Development Integrate and TestPrototype Development Time

17. 17 HW/SW Co-design and Co- verification Silicon compilation creates a single software database –One for describing hardware fabrication –One for controlling the hardware itself Specification Software Development Hardware Development Integrate and Test Prototype saving

18. 18 HW/SW Co-design and Co- verification Tools that bridge hardware and software –Co-design: develop hardware and controlling software together –Co-verification: verifying the correctness of hardware/software interface Instruction Set Simulator Bus functional model—translate high-level interface code to test vectors

19. 19 Today’s Design Flow C/C++ code Stub code Object Code HDL Test Vector/ Simulation Si Foundry DB Integrate Codesign Phase Re-spin the ASIC Iterate Software Software Process Hardware Process

20. 20 Summary The line that separates hardware and software is blurring –The design processes can be viewed as similar –The artifacts can also be viewed as similar Co-design and co-verification can reduce the development time/cost and promote better synchronization between software and hardware engineers.