1. 1 Modular Arithmetic Logic Unit By Salvador Sandoval & Lucas Morales Advisor: Dave Parent December 6, 2004

2. 2 Agenda Abstract Introduction –Reasons for selecting 4-bit ALU design –Overview of ALU design Summary of Results Project (Experimental) Details Results Cost Analysis Conclusions

3. 3 Abstract A modular Arithmetic Logic Unit was designed to operate at 200 MHz and to use less than 23W/cm 2 of power and occupy an area of less than 800 x 800  m 2. The modular ALU design will be demonstrated with a 4-bit ALU.

4. 4 To design an ALU circuit that can be used for an arbitrary number of bits. To design an n-bit ALU in a hierarchical top-down fashion. Use top- down design methodology by decomposing the ALU into one-bit slices, where slice i performs the desired functions on bits a i and b i of the operands and produces the result bit f i. Introduction B = (b n-1 …b 0 )A = (a n-1 …a 0 ) Y = (y n-1 …y 0 ) S = (s n-1 …s 0 ) ALU OPERANDS SELECT RESULT

5. 5 Introduction S0 S1 S2 C-Gen C-1 ALU OUT_0 A0B0 C0 ALU OUT_2 A1B1 C1 ALU OUT_2 A2B2 C2 ALU OUT_i AiBi CiCi-1 Each ALU block will perform the desired functions on bits a i and b i.

6. 6 Introduction Table 1. ALU Function TableALU Block Diagram Selection Code ALU S 2 S 1 S 0 Function Description 0 0 0 F = A + B Add 0 0 1 F = A - B Subtract 0 1 0 F = A + 1 Increment 0 1 1 F = A - 1 Decrement 1 0 0 F = A & B AND 1 0 1 F = A OR BOR 1 1 0 F = A Not 1 1 1 F = A  B XOR MUX OUT_i S0 S1 S2 ALU LU OUT_LU AiBi AU OUT_AU AiBi Ci

7. 7 Previous Work Previous ALU designs were designed for specific bit widths and therefore reduced design flexibility. The modular approach in our design will enable a single ALU block to be expanded for n-bits.

8. 8 Project Summary Top level ALU was decomposed into smaller modules. The smaller modules were subsequently decomposed until the entire design was represented by an interconnection of small functional modules. The ALU modules can be cascaded to create an n- bit ALU. Therefore, allowing greater reusability and flexibility.

9. 9 Project Details Results of design –Layout: Operating Frequency 178.5 MHz Power: 13.36 W/cm 2 Area: 1.75 x10 -3 cm 2 Fully Operational –Schematic: Operating Frequency 200MHz Power: 20.61 mW/cycle Fully Operational

10. 10 Longest Path Calculations Combinational Logic DelayFlip-Flop Logic Delay

11. 11 Schematic Arithmetic Logic Unit

12. 12 Schematic Arithmetic Unit

13. 13 Schematic Logic Unit

14. 14 Layout Arithmetic Logic Unit

15. 15 Layout Arithmetic Logic Unit with DFF’s

16. 16 Verification

17. 17 Verification Power = 124.098 mW/ 6-Cycles Power = 11.76W/cm2 Area = 1.75 x10 -3 cm2 Arithmetic Logic Unit Schematic

18. 18 Verification Power = 70.126 mW/ 3-Cycles Power = 13.36W/cm2 Area = 1.75 x10 -3 cm2 Arithmetic Logic Unit Layout

19. 19 Add Operation Simulations

20. 20 Simulations XOR Operation

21. 21 Simulations Subtract Operation

22. 22 Cost Analysis Time spent to project –Verifying logic = 3 hrs. –Verifying timing = 16 hrs. –Layout = 40 hrs. –Post extracted timing = 8hrs.

23. 23 Lessons Learned Take interconnect capacitance into account when designing and laying-out a circuit.

24. 24 Summary We designed a functional modular Arithmetic Logic Unit circuit. Failed to meet post extracted timing because we overlooked a few items (i.e.: interconnect capacitance, signal buffers, and signal routing) We will definitely take these items into account on future designs.

25. 25 Acknowledgements Thanks to Cadence Design Systems for the VLSI lab Thanks to Synopsys for Software donation