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MOS-AK meeting, Leuven, September 2004 University of Wales Power Device Compact Modelling Phil Mawby University of Wales Swansea
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MOS-AK meeting, Leuven, September 2004 University of Wales Outline Thermal Compact Models Electrical Compact Models MOSFET PiN Diode NPTIGBT PTIGBT Model Validation Examples
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MOS-AK meeting, Leuven, September 2004 University of Wales ET compact models of the semiconductor devices as a connection between electrical and thermal networks Physically Based Electro-Thermal Compact Modelling Approach
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MOS-AK meeting, Leuven, September 2004 University of Wales Structure diagram of the ET compact model Electro-Thermal Modelling Strategy
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MOS-AK meeting, Leuven, September 2004 University of Wales Thermal Compact Models – Thermal Networks Star-shaped resistance network
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MOS-AK meeting, Leuven, September 2004 University of Wales Extraction of the RC Thermal Network Parameters: Thermal Transient Response Function
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MOS-AK meeting, Leuven, September 2004 University of Wales Extraction of the RC Thermal Network Parameters: Thermal Transient Response Function First step is to obtain thermal transient response function of the device for a step function excitation.
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MOS-AK meeting, Leuven, September 2004 University of Wales Extraction of the RC Thermal Network Parameters: Thermal Transient Response Function 3D FEM prediction of the SML5020BN device temperature distribution after t=1000s
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MOS-AK meeting, Leuven, September 2004 University of Wales Extraction of the RC Thermal Network Parameters: Thermal Transient Response Function
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MOS-AK meeting, Leuven, September 2004 University of Wales Deconvolving above equation by the fixed function exp(z-exp(z)), Y(x) spectrum can be extracted from the transient response. Extraction of the RC Thermal Network Parameters: Deconvolution Method
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MOS-AK meeting, Leuven, September 2004 University of Wales Thermal Transient Response Function: SML5020BN MOSFET
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MOS-AK meeting, Leuven, September 2004 University of Wales Thermal Transient Response Function: STY15NA100 MOSFET
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MOS-AK meeting, Leuven, September 2004 University of Wales Cross sectional view of HEXFET The introduction of the polysilicon-gate allowed the structure to be self aligned, and allows a cellular structure which increases the packing density. This increases the active channel to total area ratio significantly compared to rectangular cell or striped structures Fairly economical process – 6/7 masks cf. 20-28 for CMOS Note whole of upper surface is coated with Source metal. This makes processing and packaging easier. Typical cell densities are greater than 2M/in 2 (300K/cm 2 ) Source contact
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MOS-AK meeting, Leuven, September 2004 University of Wales SEM of trench structure Presented ISPSD 2001 J.Zeng et.al. – Fairchild Ultra dense trench 1.1 m trench spacing – 0.18m .cm 2
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MOS-AK meeting, Leuven, September 2004 University of Wales Where does RDS(ON) come from? N - epitaxial layer Gate Source R drift R jfet R sub RaRa R chan R source R DS(ON) is made up of the series combination of all the parts of the device between the source and drain where there is a voltage drop Some of these components are negligible in some voltage ranges An approximate value can be arrived at using hand calculations. R DS(ON) = R source + R chan + R a + R jfet + R drift + R sub Drain R contact Note: all calculation carried out per unit area
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MOS-AK meeting, Leuven, September 2004 University of Wales Electrical Compact Models: Power MOSFET
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MOS-AK meeting, Leuven, September 2004 University of Wales
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MOS-AK meeting, Leuven, September 2004 University of Wales
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MOS-AK meeting, Leuven, September 2004 University of Wales Electrical Compact Models: PiN Diode Compact Model
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MOS-AK meeting, Leuven, September 2004 University of Wales PiN Diode Compact Model: Plasma Decay During Turn-off
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MOS-AK meeting, Leuven, September 2004 University of Wales PiN Diode Compact Model: Diode Turn-off
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MOS-AK meeting, Leuven, September 2004 University of Wales Electrical Compact Models: Non Punch Through IGBT Compact Model
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MOS-AK meeting, Leuven, September 2004 University of Wales Electrical Compact Models: Punch Through IGBT Compact Model
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MOS-AK meeting, Leuven, September 2004 University of Wales Electrical Compact Models: NPTIGBT and PTIGBT Compact Model Parameters ATotal IGBT active area (cm2) A DG Gate-drain overlap area (cm2) BVnBreakdown voltage index BVfBreakdown voltage multiplication constant C GS Total gate-source oxide capacitance (nF) C OXD Total gate-drain overlap oxide capacitance (nF) I LN0 Electron end leakage saturation current (A) K PLIN Transconductance in linear region (A/V2) K PSAT Transconductance in saturation region (A/V2) N D Base region doping density (cm-3) NpGaussian peak doping density (cm-3) V BI Junction built in potential (V) V TD Gate-drain overlap area threshold voltage (V) V TH Threshold voltage (V) WBase region width (cm) Channel length modulation parameter (V-1) Transverse field factor (V-1) Doping spreading factor (cm) Ambipolar lifetime (s) P Hole lifetime inside the buffer layer (s) W B Buffer layer width (cm) n F Emitter efficiency N B Buffer layer doping density (cm-3)
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MOS-AK meeting, Leuven, September 2004 University of Wales IGBT Compact Model: Clamped Inductive Load Circuit – Gate Controlled Turn-off Value for the V aa is chosen to be greater (500V) than the maximum clamping voltage V clamp (300V). Clamp inductive load circuit
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MOS-AK meeting, Leuven, September 2004 University of Wales Clamped Inductive Load Circuit – Gate Controlled Turn-off: At the beginning of the turn-off process, as soon as gate voltage decreases below V TH the MOS channel is turned-off. Then, the channel current (I ch ), which is an electron current, decreases abruptly and the anode voltage starts to rise. When the anode voltage reaches the clamp voltage (V A = V clamp ), it stays constant. The remaining current tail will decay with a longer time constant via carrier recombination and diffusion. As suggested by the arrow, the higher the clamping voltage (V clamp ) the higher will be the initial current tail size. Simulated NPTIGBT anode current and voltage turn-off waveforms
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MOS-AK meeting, Leuven, September 2004 University of Wales Clamped Inductive Load Circuit – Gate Controlled Turn-off: Carrier concentration at the left (anode) plasma edge decay during NPTIGBT turn-off - carrier concentration decreases monotonically during turn-off
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MOS-AK meeting, Leuven, September 2004 University of Wales Clamped Inductive Load Circuit – Gate Controlled Turn-off: Simulated PTIGBT anode current and voltage turn-off waveforms – PTIGBT has a shorter turn-off time than a corresponding NPTIGBT since the carriers are cleared away from the PTIGBT base by the depletion region as it reaches the buffer layer.
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MOS-AK meeting, Leuven, September 2004 University of Wales IRG4BC20UD (International Rectifier) IGBT Anode current and voltage turn-on waveforms Anode current and voltage turn-off waveforms
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MOS-AK meeting, Leuven, September 2004 University of Wales ET PiN Diode Simulation
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MOS-AK meeting, Leuven, September 2004 University of Wales ET PiN Diode Simulation Anode Current vs. time Anode Voltage vs. time
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MOS-AK meeting, Leuven, September 2004 University of Wales Step-Up Converter: Schematic of an Electro-Thermal Model f=20kHz
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MOS-AK meeting, Leuven, September 2004 University of Wales Step-Up Converter: Drain Voltage Vs. Time
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MOS-AK meeting, Leuven, September 2004 University of Wales Step-Up Converter: Output Voltage and Junction Temperature
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MOS-AK meeting, Leuven, September 2004 University of Wales Synchronous Buck Converter: Topology and Typical Power Losses
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MOS-AK meeting, Leuven, September 2004 University of Wales Isolated Forward Converter: Topology and Typical Power Losses
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MOS-AK meeting, Leuven, September 2004 University of Wales Conclusions MOSFET model is simple cf. deep sub micron Electro Thermal interactions are key Bipolar Plasma modelling is very challenging Long real times for simulations
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MOS-AK meeting, Leuven, September 2004 University of Wales Aknowledgement Thanks to Dr.P.Igic
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