1. Pin-Outs for Additional Hardware 7 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 5 6 First 30 pins from connector A2 Second 2 pins from connector A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 I/O RD I/O WR TXE RXF DLP-USB245M Pins 13-24 are connected to FPGA pins 7 through 18 of connector A1

2. Input Conditioning (Serial to Parallel Conversion)

3. Output Conditioning (Parallel to Serial Conversion)

4. Output Subsystem

5. Input Subsystem

6. Dual Buffer Layout

7. USB Design Logic

8. SignalDescription CLKSystem Clock RSTAsynchronous active-high reset. Din[7:0]Eight-bits Data From Buffer LDLoad pulse to load Din in the Transmitter and start the transmission RxRS232 receive signal input. Is ’1’ when the line is idle. TxRS232 transmit signal output. Is ’1’ when the line is idle. Dout[7:0]Data received. RxRDYA ‘1’ pulse (one system clock cycle long) indicates that a character is received and is available at Dout. TxBusyIndicates that the UART is busy sending data. Will ignore any LD request. SDin[7:0] / SDout[7:0]Data received from RS-232 BuffDin[7:0] / BuffDout[7:0]Data From dual buffer, to be transmitted by UART WriteBuff / ReadBuffControl signal to write or read to/from Dual Buffer BuffFull / BuffEmptyIndicates if Buffers are Full or Empty. UART System