1. 1 Level1 Central Track Trigger Physics Justification Proposed Implementation Costs and Schedule Meenakshi Narain Boston University / Dzero Collaboration Run2b trigger meeting, April 25 th, 2002 Summary of work done in the Run2b L1CTT group Results from: Graham Wilson, Liang Han, Mike Hildredth, +input from Terry Wyatt, Marvin Johnson, Fred Borcherding, U. Heintz

2. 2 Level1 Central Track Trigger Goals: –provide stand-alone track triggers –combine tracking and preshower information to identify electron and photon candidates –generating track lists that allow other trigger systems to perform track matching. A critical part of the L1 muon trigger (current design) Match tracks to L1 calorimeter candidates to identify electrons and taus (proposed upgrade) Used in Level2 –for identifying high pT electrons and muons candidates. –The L2 Silicon Track Trigger (STT) uses these tracks for finding displaced tracks in the Silicon Microstrip Tracker which are from b-quark decays. The CTT therefore aims to provide tracks down to pT  1.5 GeV.

3. 3 Current Run2a Implementation Uses Central Fiber Tracker and preshowers Divide into 80 sectors (each 4.5 o ) Track Finding: –Define hits from using pairs of fiber in each axial layer (doublets) –Compare doublet hits with predefined patterns to validate a track –Use 4 independent pT bins (Thresholds = 1.5, 3, 5, 10) –Find tracks in each bin

4. 4 Tracking Trigger Feed all axial fibers plus preshower into gate arrays Trigger if a fiber combination is consistent with P T > (1.5,3,5,10) GeV Tag categories (incl. CPS info): track, isolated track, electron,... Trigger response for Z  ee MC with 4 min.bias overlayed Red lines: triggered tracks from Z

5. 5 Why Upgrade? Expected Run 2A performance: –97% of muons with pT > 50 GeV/c are reconstructed correctly –Of the remaining 3%, 1.9% of the tracks are not reconstructed at all –1.1% are reconstructed as two tracks due to detector noise Expected Run2B performance: –Significantly more challenging due to increased number of minimum bias interactions (4-5). –Tracking trigger rate is expected to rise dramatically due to accidental hit combinations yielding fake tracks. –The 5 GeV threshold track trigger is satisfied in more than 12% of beam crossings with 5 minbias interactions !

6. 6 Why Upgrade? Run2b trigger rates with the current design are strongly dependent upon the number of underlying minimum bias An increasingly compromised tracking trigger with luminosity! Trigger rate for one track with pT > 10 GeV Probability for specific track trigger terms to be satisfied in a given crossing 400KHz

7. 7 Paths for improvement… A possible solution: –The fiber doublet is larger than the fiber diameter, which results in a widening of the effective width of a fiber to that of a doublet, decreasing the resolution of the hits that are used for track finding. –Use individual fiber hits rather than doublets –Inherently narrower and therefore has a reduced probability of selecting a random combination of hits Fiber 1Fiber 2Fiber 3Doublet 1000 1010 1100 1110 0000 0011 0101 0111

8. 8 Paths for improvement… Use different schemes to get efficiency and rejections. Schemes: –all-singlet case (16 layers) –mixed schemes some CFT layers are treated as pairs of singlet layers and the rest as doublets. Notation: –Upper case  hits treated as doublets –lower case  singlet hits. – ABCDEFGH : 8 layers of doublets Run 2a CTT scheme – abcdefgh: 16 layers of singlets. Geometrical acceptance for hit requirement in the 16-trigger layer configuration. # of hits  8  11  12  13 track sagitta, s = 0.02*e/ pT

9. 9 Different Equation Schemes Default Doublet Equations 16-Layer Singlet Equations 12-Layer Equations “abcdEFGH” 12-Layer Equations ”ABCDefgh” 14-Layer Equations abcdefGH Efficiency for p T >1096.999.398.6 97.399.2 Efficiency for 5< p T <10 91.197.892.890.891.6 Efficiency for fake p T >10 5.80.41.61.40.7 Efficiency for fake 5< p T <10 8.00.72.4 1.6 Fake TTK(2,10)0.700.13 00.03 Fake TTK(1,5)12.11.13.7 2.2 Fake TTK(2,5)2.20.050.4 0.080.13 Single muons overlaid on events containing exactly six minimum bias interactions and put through the detailed DØ simulation and the modified trigger simulator.

10. 10 Diff Schemes: # of Equations Factor of 10 for 12singlets/2doublets Factor of 4-5 for 8singlets/4 doublets Singlet/Doublet SchemeRelative # of equations Average number of terms/equation All doubletsABCDEFGH1.08 All singletsabcdefgh15.312.6 2 doublets 12 singlets abCdeFgh10.511.4 ABcdefgh10.011.4 abcdefGH7.711.4 4 doublets 8 singlets ABCDefgh5.710.3 aBcDeFgH5.610.2 abcdEFGH4.210.2

11. 11 Effect of Inefficiencies Inefficiencies tend to cause explosion in number of equations. use npe=8, threshold=1.5 For 16 singlet layer equations:

12. 12 A viable scheme pT threshold (GeV) EfficiencyDoublet /singlet scheme Resources relative to total Run 2A resources pT > 2098%abcdefgh28 x 1.5 x 0.075 = 3.15 pT > 1098%abcdefgh28 x 1.5 x 0.075 = 3.15 pT > 595%abcdefGH6.2 x 1.4 x 0.2 = 1.3 pT > 1.595%abcdEFGH3.0 x 1.2 x 0.5 = 2.5 Use 16 singlet layer for high pT bin keeping high efficiency Use 12 singlets and 2 doublet layers for low pT bins and accept lower efficiency A factor of 10 more resources needed compared to Run2A

13. 13 Run2A L1CTT Implementation System: 7 crates, 3 separate chains: axial tracker & central preshower DFEA - CTOC - CTTT - MTM - L1FW (with L2 sidechain CTOC - CTQD - L2CTT) Forward Preshower DFEF - FPSS - FPTT - MTM -L1FW (with L2 side chain FPSS - L2FPS) Central Preshower stereo DFES-CPSS-L2CPS chain (Level 2 only) Common Motherboard

14. 14 Digital Daughter board Digital Board daughter cards come in two flavors: –single width for Axial trigger (DFEA) –double width for everything else : DFEF, DFES, Collector ('octet') cards CTOC Concentrator ('singlet') cards CTTT. etc… DFE Daughtercard Rebuild DFEA boards Replace FPGAs Common Motherboard No changes needed

15. 15 Compare FPGA resources FPGA # Logic Cells: Run2a (Xilinx Virtex series) –XCV40010,800 (med, lo, hi) –XCV60015,552 (lowest pT) Run2b (Xilinx VirtexII series) –XC2V600076,032 (2 low pT) –XC2V8000104,832 (2 hi pT)  Can accommodate factor of 6 – 10 more resources compared to Run2a.

16. 16 FPGA Costs and Availability Proposed “Run2B’ FPGA: –XC2V6000- 2 low pT bins($900 each) –XC2V8000 - 2 high pT bins ($2000 each) –Cost projections include 10% price reduction per quarter and procurement in Dec’03. Footprint of these VirtexII series FPGA are different  new Daughter cards (DFEA) Motherboards and all other daughter boards remain the same

17. 17 Cost *  25% contingency

18. 18 Groups Simulation and Algorithm development: –Brown –Kansas –Manchester –Notre Dame Hardware: –Boston University –FNAL

19. 19 Schedule Description of TaskCompletion Date Prototype algorithm simulated using FPGA simulation tools11/5/02 Target algorithm coded and simulated6/11/03 Layout Prototype I boards8/7/03 Develop test procedures7/24/03 Assemble and test prototype I12/2/03 Layout prototype II boards11/21/03 Assemble and test prototype II2/27/04 Test prototype II at FNAL with the full test chain1/30/04 Design, Layout and Fabricate production boards4/23/04 Daughter boards tested and ready for installation11/3/04 Install and commission the trigger6/1/05

20. 20 Fallback Options lowest pT bin: prune eqns tighter, give up on extended pT, all of this coupled to performance of STT and needs to be studied. Keep very high eff only for 2 high pT bins only Alternative algorithm being considered (uses less equations – a more dynamic/computational approach)

21. 21 Operations at 396ns Red: 16 layer scheme and Green: 8 layer scheme Rejection for 396 ns in Run2b (15 minbias events) with 16 layer scheme will be almost similar to 8 layer with 5 minbias events