1. Slides to Accompany a Video Tutorial on Harry Porter’s Relay Computer Harry Porter, Ph.D. Portland State University November 7, 2007

2. +V

3. Double Throw Relay

4. +V Double Throw Relay

5. Four Pole, Double Throw Relay

6. +V Four Pole, Double Throw Relay

8. Schematic Diagrams Assume other terminal is connected to ground

9. Schematic Diagrams Assume other terminal is connected to ground +V

10. The “NOT” Circuit inout in out +V in out 0 1 1 0 0 1 Convention: “1” = +12V “0” = not connected

11. The “NOT” Circuit inout in out +V in out 0 1 1 0 1 0 Convention: “1” = +12V “0” = not connected

12. c The “OR” Circuit b b or c +V b c OUT 0 0 0 0 1 1 1 0 1 1 1 1 b c b or c

13. An Optimization? c b b or c b c

14. c An Optimization? b b or c b c c or d d d

15. c An Optimization? b b or c b c c or d d d Whoops!

16. An Optimization? b or c c b +V d c or d b b or c c c or d d

17. 1-Bit Logic Circuit b c NOT b c NOT AND OR XOR 0 0 1 0 0 0 0 1 1 1 0 0 0 1 1 1 1 0 AND OR XOR

18. 1-Bit Logic Circuit b V NOT AND OR XOR c b c NOT AND OR XOR 0 0 1 0 0 0 0 1 1 1 0 0 0 1 1 1 1 0

19. 1-Bit Logic Circuit b V c NOT AND OR XOR b c NOT AND OR XOR 0 0 1 0 0 0 0 1 1 1 0 0 0 1 1 1 1 0

20. 1-Bit Logic Circuit b V c NOT AND OR XOR b c NOT AND OR XOR 0 0 1 0 0 0 0 1 1 1 0 0 0 1 1 1 1 0

21. 1-Bit Logic Circuit b V c NOT AND OR XOR b c NOT AND OR XOR 0 0 1 0 0 0 0 1 1 1 0 0 0 1 1 1 1 0

22. 1-Bit Logic Circuit b V c NOT AND OR XOR b c NOT AND OR XOR 0 0 1 0 0 0 0 1 1 1 0 0 0 1 1 1 1 0

23. AND 7 OR 7 Eight 1-bit circuits can be combined to build an... 8-Bit Logic Circuit Logic Circuit NOT 7 B7B7 C7C7 XOR 7 AND 1 OR 1 Logic Circuit NOT 1 B1B1 C1C1 XOR 1 AND 0 OR 0 Logic Circuit NOT 0 B0B0 C0C0 XOR 0

24. The “Full Adder” Circuit Carry in Carry out Full Adder Sum BC Cy in B C Cy out Sum 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1

25. 8 full-adders can be combined to build an... 8-Bit Adder Carry Full Adder Full Adder B0B0 C0C0 Sum 0 Sum 1 B1B1 C1C1 Carry Full Adder Sum 7 B7B7 C7C7 + B 8 8 8 C Sum Carry 0

26. The Zero-Detect Circuit Result Bus Zero V+

27. The Zero-Detect Circuit Result Bus Zero V+ Sign

28. Enable Circuit Enable

29. Enable Circuit x7x7 x6x6 x5x5 x4x4 x3x3 x2x2 x1x1 x0x0 Result Bus B XOR C Enable

30. Enable Shift Left Circular (SHL) b7b7 b6b6 b5b5 b4b4 b3b3 b2b2 b1b1 b0b0 Result Bus B

31. 3-to-8 Decoder f1f1 V f0f0 f2f2 INC AND OR XOR NOT SHL ADD f 0 f 1 f 2 OUTPUT 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 1

32. Carry Sign Arithmetic Logic Unit (ALU) B 8 8 8 C Data Bus 3 Zero 8-bit Logic 8-bit Adder EnableEn AND OR XOR NOT SHL INC ADD Function 3-to-8 Decoder Zero-Detect

33. Carry Sign An 8-Bit ALU ALU B 8 8 8 C Result Function Code 000 add 001 inc 010 and 011 or 100 xor 101 not 110 shl 111 3 Zero

34. Register Storage +V A

35. Register Storage +V A7A7 A0A0 A6A6

36. Register Storage +V Bus Enable A7A7 A0A0 A6A6 Select

37. Register Storage A7A7 Select Load A0A0 Enable A6A6 Bus

38. Register Storage A7A7 Select Load A0A0 Enable A6A6 Bus

39. 8-Bit “Data” Bus Load Select Load Select “X” Register “Y” Register 8-Bit Registers

40. 16-Bit “Address” Bus 8-Bit “Data” Bus “X” Register “Y” Register Load Select Load Select Load Select

41. 16-bit Increment Inst M1M1 M2M2 M X Y XY J1J1 J2J2 J PC Inc 8-bit ALU Memory Addr Data ZCyS System Architecture 8-bit Data Bus A B C D 16-bit Address Bus

42. 32K Byte Static RAM Chip LEDs 8 FET Power Transistors (to drive relays during a memory-read operation)

43. 16-bit Increment Inst M1M1 M2M2 M X Y XY J1J1 J2J2 J PC Inc 8-bit ALU Memory Addr Data ZCyS 8-bit Data Bus A B C D 16-bit Address Bus Example: The ALU Instruction

44. 16-bit Increment Inst M1M1 M2M2 M X Y XY J1J1 J2J2 J PC Inc 8-bit ALU Memory Addr Data ZCyS Step 1: Fetch Instruction 8-bit Data Bus A B C D MEM-READ SELECT LOAD 16-bit Address Bus

45. Inst M1M1 M2M2 M X Y XY J1J1 J2J2 J PC Inc 8-bit ALU Memory Addr Data ZCyS 8-bit Data Bus A B C D Step 2: Increment PC SELECT LOAD 16-bit Increment 16-bit Address Bus

46. 16-bit Increment Inst M1M1 M2M2 M X Y XY J1J1 J2J2 J PC Inc 8-bit ALU Memory Addr Data ZCyS 8-bit Data Bus A B C D LOAD SELECT Step 3: Update PC 16-bit Address Bus

47. 16-bit Increment Inst M1M1 M2M2 M X Y XY J1J1 J2J2 J PC Inc Memory Addr Data ZCyS 8-bit Data Bus A D Step 4: Execute Instruction FUNCTION LOAD B C 8-bit ALU 16-bit Address Bus

48. Clock Switch +V Output +V

49. Clock Switch +V Output +V Charging

50. Clock Switch +V Output +V Discharging

51. Clock Switch +V Output +V

52. Clock +V A BCD

53. Clock Charging +V On Discharging A BCD

54. +V Clock Charging +V On Discharging On A BCD

55. +V Clock Charging +V On Discharging On A BCD

56. +V Clock Charging +V On Discharging On A BCD

57. +V Clock Charging +V On Discharging On A BCD

58. Clock Timing Diagram A B C D Clock Clock = (A and B) or (C and D)

59. t7t7 t5t5 t4t4 t3t3 t2t2 t1t1 Finite State Machine 12345678 t6t6 t8t8 Outputs clock

60. Output from FSA 2345678123456781231 t1t1 t2t2 t3t3 t4t4 t5t5 t6t6 t7t7 t8t8

61. Instruction Timing - ALU Instruction Select PC Memory Read Load Instr Load Inc Select Inc Load PC ALU Function Load A Load Cond.Code Reg. 2345678123456781231

62. Instruction Timing - ALU Instruction Select PC Memory Read Load Instr Load Inc Select Inc Load PC ALU Function Load Cond.Code Reg. 2345678123456781231 Fetch Load A

63. Instruction Timing - ALU Instruction Select PC Memory Read Load Instr Load Inc Select Inc Load PC ALU Function Load Cond.Code Reg. 2345678123456781231 Increment Load A

64. Instruction Timing - ALU Instruction Select PC Memory Read Load Instr Load Inc Select Inc Load PC ALU Function Load Cond.Code Reg. 2345678123456781231 Load A Execute

65. Instruction Decoding Instruction RegisterFinite State Machine Control Signals (Load, Select, Mem-Read, etc.) Combinational Logic 123456 765432 10

66. 12345678910 Instruction Timing - 16-bit Move Select PC Memory Read Load Instr Load Inc Select Inc Load PC Select Source-Register 234567811 Load Dest-Register (Same as before)

67. Finite State Machine 1234567 911131516 17181920212223 101214 24 8

68. Instruction Decoding and Control Clock Instruction Register Finite State Machine Control Lines Instruction Decoding Data Bus

69. The Instruction Set 0 0 d d d s s s1 0 0 0 r f f f0 1 r d d d d d1 0 1 1 0 0 0 0 Move ALU Load Immediate 16-bit Increment ddd = destination register sss = source register (A, B, C, D, M 1,M 2,X or Y) r = destination register (A or D) fff = function code (add, inc, and, or, xor, not, shl) r = destination register (A or B) ddddd = value (-16..15) XY  XY + 1

70. The Instruction Set 1 0 0 1 0 0 r r1 0 0 1 1 0 r r1 1 0 0 0 0 0 01 0 1 0 1 1 1 0 Load Store Load 16-bit Immediate Halt rr = destination register (A, B, C, D) reg  [M] rr = source register (A, B, C, D) [M]  reg Load the immediate value into M (i.e., M 1 and M 2 ) v v v v

71. The Instruction Set 1 1 1 0 0 1 1 01 0 1 0 d s s 01 0 1 0 Goto Call 16-Bit Move Return / Branch Indirect a a a a Branch to the given address 1 1 1 0 0 1 1 1a a a a Branch to the given address Save return location in XY register PC  XY d = destination register (PC or XY) ss = source register (M, XY or J)

72. The Instruction Set 1 1 1 1 0 0 0 0 Branch If Negative Branch If Carry Branch If Zero Branch If Not Zero a a a a Branch to the given address if S = 1 1 1 1 0 1 0 0 0a a a a Branch to the given address if Cy = 1 Branch to the given address if Z = 1 Branch to the given address if Z = 0 1 1 1 0 0 1 0 0a a a a 1 1 1 0 0 0 1 0a a a a

73. An Example Program address instr assembly comment 0000 0000 0011 1001 Y=B Y  B 0000 0001 0011 0110 X=0 X  0 0000 0010 1000 0101 A=¬B If sign(Y)==1 0000 0011 1111 0000 BNEG Else. 0000 0100 0000 0000.. 0000 0101 0000 0111.. 0000 0110 0011 0010 X=C X  C Else:. 0000 0111 0101 1001 A=-7 D  -7 0000 1000 0001 1000 D=A. Loop: Loop: 0000 1001 0000 1110 B=X Shift X left (circular) 0000 1010 1000 0110 A=B<<1. 0000 1011 0011 0000 X=A. 0000 1100 0000 1111 B=Y Shift Y left (circular) 0000 1101 1000 0110 A=B<<1. 0000 1110 0011 1000 Y=A. 0000 1111 0000 1111 B=Y If sign(Y)==1 0001 0000 1000 0101 A=¬B. 0001 0001 1111 0000 BNEG Else2. 0001 0010 0000 0000.. 0001 0011 0001 0111.. 0001 0100 0000 1110 B=X X  X + C 0001 0101 1000 0000 A=B+C. 0001 0110 0011 0000 X=A. Else2:. 0001 0111 0000 1011 B=D D  D + 1 0001 1000 1000 1001 D=B+1. 0001 1001 1110 0010 BNZ Loop If D != 0 goto Loop 0001 1010 0000 0000.. 0001 1011 0000 1001.. 0001 1100 1010 1110 HALT HALT