1. Counters as State Machines Lecture L9.1 Handout Section 9.1

2. Counters as State Machines Divide by 8 Counter A Divide-by-16 Counter with Count Enable

3. CLK DQ !Q CLK DQ !Q CLK DQ !Q Q0Q0.D Q1 Q2 Q1.D Q2.D s0 0 0 0 0 0 1 s1 0 0 1 0 1 0 s2 0 1 0 0 1 1 s3 0 1 1 1 0 0 s4 1 0 0 1 0 1 s5 1 0 1 1 1 0 s6 1 1 0 1 1 1 s7 1 1 1 0 0 0 State Q2 Q1 Q0 Q2.D Q1.D Q0.D Divide-by-8 Counter

4. s0 0 0 0 0 0 1 s1 0 0 1 0 1 0 s2 0 1 0 0 1 1 s3 0 1 1 1 0 0 s4 1 0 0 1 0 1 s5 1 0 1 1 1 0 s6 1 1 0 1 1 1 s7 1 1 1 0 0 0 State Q2 Q1 Q0 Q2.D Q1.D Q0.D Divide-by-8 Counter Q2 Q1 Q0 00011110 0 1 11 1 1 Q2.D Q2.D = !Q2 & Q1 & Q0 # Q2 & !Q1 # Q2 & !Q0

5. s0 0 0 0 0 0 1 s1 0 0 1 0 1 0 s2 0 1 0 0 1 1 s3 0 1 1 1 0 0 s4 1 0 0 1 0 1 s5 1 0 1 1 1 0 s6 1 1 0 1 1 1 s7 1 1 1 0 0 0 State Q2 Q1 Q0 Q2.D Q1.D Q0.D Divide-by-8 Counter Q2 Q1 Q0 00011110 0 1 1 1 1 1 Q1.D Q1.D = !Q1 & Q0 # Q1 & !Q0

6. s0 0 0 0 0 0 1 s1 0 0 1 0 1 0 s2 0 1 0 0 1 1 s3 0 1 1 1 0 0 s4 1 0 0 1 0 1 s5 1 0 1 1 1 0 s6 1 1 0 1 1 1 s7 1 1 1 0 0 0 State Q2 Q1 Q0 Q2.D Q1.D Q0.D Divide-by-8 Counter Q2 Q1 Q0 00011110 0 1 1 1 1 1 Q0.D Q0.D = ! Q0

7. Divide-by-8 Counter A state machine for a divide by 8 counter

8. Divide-by-8 Counter A state-transition table s0 0 0 0 0 0 1 s1 0 0 1 0 1 0 s2 0 1 0 0 1 1 s3 0 1 1 1 0 0 s4 1 0 0 1 0 1 s5 1 0 1 1 1 0 s6 1 1 0 1 1 1 s7 1 1 1 0 0 0 State Q2 Q1 Q0 Q2.D Q1.D Q0.D

9. Divide-by-8 Counter A Divide by 8 counter Circuit using D Flip-flops

10. MODULE div8cnts TITLE 'Divide by 8 Counter using State Machine' DECLARATIONS hex7seg interface([D3..D0] -> [a,b,c,d,e,f,g]); d7R FUNCTIONAL_BLOCK hex7seg; " INPUT PINS " CLK PIN 12; " 1 Hz clock (jumper) clear PIN 11;" switch 1 " OUTPUT PINS " Q2..Q0 PIN 41,43,44 ISTYPE 'reg'; " LED 14..16 Q = [Q2..Q0]; " 3-bit output vector [a,b,c,d,e,f,g] PIN 15,18,23,21,19,14,17 ISTYPE 'com'; " Rightmost (units) 7-segment LED display div8cnts.abl

11. " Definitions QSTATE = [Q2,Q1,Q0]; s0 = [0,0,0]; s1 = [0,0,1]; s2 = [0,1,0]; s3 = [0,1,1]; s4 = [1,0,0]; s5 = [1,0,1]; s6 = [1,1,0]; s7 = [1,1,1]; state_diagram QSTATE state s0: GOTO s1; state s1: GOTO s2; state s2: GOTO s3; state s3: GOTO s4; state s4: GOTO s5; state s5: GOTO s6; state s6: GOTO s7; state s7: GOTO s0; Define the states; Associate a variable name With a numerical representation Define the transitions between the states div8cnts.abl (cont.)

12. EQUATIONS Q.AR = clear; Q.C = CLK; [a,b,c,d,e,f,g] = d7R.[a,b,c,d,e,f,g]; d7R.[D2..D0] = Q; d7R.D3 = 0; Connect the clock Connect the 7-segment display div8cnts.abl (cont.)

13. test_vectors([CLK, clear] -> Q) [.C.,1] -> 0; [.C.,0] -> 1; [.C.,0] -> 2; [.C.,0] -> 3; [.C.,0] -> 4; [.C.,0] -> 5; [.C.,0] -> 6; [.C.,0] -> 7; [.C.,0] -> 0; [.C.,0] -> 1; [.C.,0] -> 2; [.C.,0] -> 3; [.C.,0] -> 4; END div8cnts

14. Counters as State Machines Divide by 8 Counter A Divide-by-16 Counter with Count Enable

15. count = 1 Counter counts count = 0 Counter stops counting Cout = 1 if [Q3..Q0] = [1,1,1,1]

16. State Diagram for a Divide-by-16 Counter with Count Enable

17. div16cnt.abl MODULE div16cnt interface ([CLK,clear,count] -> [Q3,Q2,Q1,Q0,Cout]); TITLE 'Divide by 16 (4-bit) Counter using State Machine' DECLARATIONS " INPUT PINS " CLK PIN ; " clock input clear PIN ;" asynchronous clear count PIN ;" count enable " OUTPUT PINS " Q3..Q0 PIN ISTYPE 'reg'; Q = [Q3..Q0]; " 3-bit output vector CoutPIN ISTYPE 'com';" Carry out

18. " Definitions QSTATE = [Q3,Q2,Q1,Q0]; s0 = [0,0,0,0]; s1 = [0,0,0,1]; s2 = [0,0,1,0]; s3 = [0,0,1,1]; s4 = [0,1,0,0]; s5 = [0,1,0,1]; s6 = [0,1,1,0]; s7 = [0,1,1,1]; s8 = [1,0,0,0]; s9 = [1,0,0,1]; s10 = [1,0,1,0]; s11 = [1,0,1,1]; s12 = [1,1,0,0]; s13 = [1,1,0,1]; s14 = [1,1,1,0]; s15 = [1,1,1,1]; div16cnt.abl (cont.)

19. state_diagram QSTATE state s0: if count then s1 else s0; state s1: if count then s2; else s1; state s2: if count then s3; else s2; state s3: if count then s4; else s3; state s4: if count then s5; else s4; state s5: if count then s6; else s5; state s6: if count then s7; else s6; state s7: if count then s8; else s7; Use If..Then statements to implement the count div16cnt.abl (cont.)

20. state s8: if count then s9 else s8; state s9: if count then s10; else s9; state s10: if count then s11; else s10; state s11: if count then s12; else s11; state s12: if count then s13; else s12; state s13: if count then s14; else s13; state s14: if count then s15; else s14; state s15: if count then s0; else s15;

21. div16cnt.abl (cont.) EQUATIONS Q.C = CLK; Q.AR = clear; Cout = Q3 & Q2 & Q1 & Q0; END div16cnt

22. 8-Bit Counter