1. How to use the VHDL and schematic design entry tools.

2. ABSTRACT Demonstrates how to create a top-level schematic that contains instantiations of the modules, and describe how to wire together the modules, and determine the circuit behavior by computer simulation.

3. Starting the Xilinx’s Software For PC users, start Xilinx program from the Start menu by selecting the following path: Start  Programs  Xilinx Foundation Series 2.1i  Project Manager

4. Creating New Project Select OK New Project dialog box comes out Give “ Name ”— Lab5; create the directory path — a:\lab5; Select OK

5. Creating a New Schematic Click on the third item named Schematic Editor in the first flow chart box. Schematic Editor

6. Schematic Editor Window Symbol Toolbox

7. Libraries Click on the Symbols Toolbox icon Click on Select Libraries

8. Instantiating VHDL Modules Select FJKSRE from the SC Symbols Window. Place four FJKSREs in the schematic editor window by simply dragging from the SC Symbols Window.

9. Instantiating VHDL Modules Similarly select AND2. Place three AND2’s in the Schematic Editor Window.

10. Instantiating VHDL Modules Place one inverter in the Schematic Editor Window. Select VCC and GND and place it on the Schematic Editor Window.

11. Adding Hierarchy Connectors Click on the Hierarchy Connector Symbol.

13. Wiring the Components Go to the left toolbar and click on Draw wires Symbol. To make a connection: 1. Click once at the vertex of a pin; 2. Extend the wire to the desired length; 3. Click on the location you want the wire to terminate. Draw Wires

14. Simulation Click on the Simulator button in the taskbar on the top of the workspace. Simulator

15. Simulation Inside the Waveform Viewer Window click on Add Signals. Double Click

16. Setting the Field Values Click on the text that says Clock, then click on the Select Simulator button in the Waveform Viewer Window. Select Simulators Click Double Click Click

17. Setting the Field Values Click on the text that says Reset, then click the Logic States Button. Logic States Click Simulation Step

18. Final Output

19. Reference Lab Manual