1. ENGIN 112 Intro to Electrical and Computer Engineering Lecture 32 Hazards
Give qualifications of instructors:
DAP
teaching computer architecture at Berkeley since 1977
Co-athor of textbook used in class
Best known for being one of pioneers of RISC
currently author of article on future of microprocessors in SciAm Sept 1995 RY
took 152 as student, TAed 152,instructor in 152
undergrad and grad work at Berkeley
joined NextGen to design fact 80x86 microprocessors
one of architects of UltraSPARC fastest SPARC mper shipping this Fall

2. Minimum sum of products implementation reduces costs
Overview
Minimum sum of products implementation reduces costs
Propagation delays in circuits can lead to output glitches
Hazards can be determined from K-map
Technique using K-maps to avoid hazards
Look for neighboring circles
Hazards are less of a concern for sequential circuits.
Combinational outputs settle prior to rising clock edge
credential:
bring a computer
die photo
wafer :
This can be an hidden slide. I just want to use this to do my own planning.
I have rearranged Culler’s lecture slides slightly and add more slides. This covers everything he covers in his first lecture (and more) but may
We will save the fun part, “ Levels of Organization,” at the end (so student can stay awake): I will show the internal stricture of the SS10/20.
Notes to Patterson: You may want to edit the slides in your section or add extra slides to taylor your needs.

3. There is a finite propagation delay through all gates.
Combinational Delay
Logic gates do not produce an output simultaneously with a change in input.
There is a finite propagation delay through all gates.
input output
input
output
time
propagation delay

4. Example of Combinational Hazards
Eg. Q = AB’ + BD if B & D are 1 then Q should be 1 but because of propagation delays, if B changes state then Q will become unstable for a short time, as follows: A B D Q
(C)
Q goes low for a short time even though the function says that it should be independent of B when both A & D are high. A D B
(C) Q
High
glitch

5. Hazards/glitches: unwanted switching at the outputs
Occur when different paths through circuit have different propagation delays
Dangerous if logic causes an action while output is unstable
May need to guarantee absence of glitches
Usual solutions
1) Wait until signals are stable (by using a clock): preferable (easiest to design when there is a clock – synchronous design)
2) Design hazard-free circuits

6. Types of Hazards Static 1-hazard Static 0-hazard Dynamic hazards
Input change causes output to go from 1 to 0 to 1
Static 0-hazard
Input change causes output to go from 0 to 1 to 0
Dynamic hazards
Input change causes a double change from 0 to 1 to 0 to 1 OR from 1 to 0 to 1 to 0 1 1 1 1

7. Hazard Elimination
Hazards like these are best eliminated logically. The Karnaugh Map of the required function gives one method.
Covering the hazard causing the transition with a redundant product term (AD) will eliminate the hazard. The hazard free Boolean equation is:
Q = AB’+BD+AD D AB
AB’ BD AD

8. Static Hazards
Due to a literal and its complement momentarily taking on the same value
Thru different paths with different delays and reconverging
May cause an output that should have stayed at the same value to momentarily take on the wrong value
Example F A B S S'
hazard
static-0 hazard
static-1 hazard

9. Due to the same versions of a literal taking on opposite values
Dynamic Hazards
Due to the same versions of a literal taking on opposite values
Thru different paths with different delays and reconverging
May cause an output that was to change value to change 3 times instead of once
Example: A C A C B F 1 2 3 B1 B2 B3 F
hazard
dynamic hazards

10. Hazard Example
Logic gates do not produce an output simultaneously with a change in input.
There is a finite propagation delay through all gates.

11. Hazard Removal for Static 0
Locate boundaries between circles
Add an extra circle (product term) to eliminate hazard
Note: addition of term does not lead to minimum sum of products implementation.

12. Hazard Removal Result
Addition of extra AND gate and extra OR gate input
Generally does not slow down circuit
Not as important for sequential circuits

13. When inputs change, intermediate values created
Summary
When inputs change, intermediate values created
Could lead to incorrect circuit behavior
Hazards can be determined from K-map
Technique using K-maps to avoid hazards
Use additional implicants
Hazards not as important for sequential design
Hazard removal requires additional hardware
credential:
bring a computer
die photo
wafer :
This can be an hidden slide. I just want to use this to do my own planning.
I have rearranged Culler’s lecture slides slightly and add more slides. This covers everything he covers in his first lecture (and more) but may
We will save the fun part, “ Levels of Organization,” at the end (so student can stay awake): I will show the internal stricture of the SS10/20.
Notes to Patterson: You may want to edit the slides in your section or add extra slides to taylor your needs.