Presentation is loading. Please wait.

Presentation is loading. Please wait.

Courseware Path-Based Scheduling Sune Fallgaard Nielsen Informatics and Mathematical Modelling Technical University of Denmark Richard Petersens Plads,

Similar presentations


Presentation on theme: "Courseware Path-Based Scheduling Sune Fallgaard Nielsen Informatics and Mathematical Modelling Technical University of Denmark Richard Petersens Plads,"— Presentation transcript:

1 courseware Path-Based Scheduling Sune Fallgaard Nielsen Informatics and Mathematical Modelling Technical University of Denmark Richard Petersens Plads, Building 322 DK2800 Lyngby, Denmark

2 SoC-MOBINET courseware[M-1] High Level Synthesis2 Overview  Motivation  Introduction – Prior work / new paradigm  Defining problem and model constraints  Solution:  AFAP Scheduling  Algorithm  The scheduling steps using AFAP  Results  Conclussion

3 SoC-MOBINET courseware[M-1] High Level Synthesis3 Motivation Derive a synthesis tool which:  Minimizes the number of control steps  Takes constraints into account  Considers loops and conditional branches ( which no prior work has done )

4 SoC-MOBINET courseware[M-1] High Level Synthesis4 Introduction  Prior work: scheduling <- minimize cost function  Cost function: - Fixed hardware (uP): Number of states - Hardware syntheses: Number of states + hardware  Scheduling: Minimizing the cost function by moving operations around  Optimal solution: - Optimal schedule emphasizing concurrency - Force directed serialization + moving mobile operations

5 SoC-MOBINET courseware[M-1] High Level Synthesis5 Introduction / Problem  Path-Based Scheduling for Synthesis:  Forget cost functions!  Instead: Emphasize on conditional branches, loops  Minimize number of control steps - taking constraints into account ( main problem )  Main problem: Gain advantages from looking at branches

6 SoC-MOBINET courseware[M-1] High Level Synthesis6 Constraints  Internal constraints: -Units can only receive and output values once per cycle -With single phase clock this implies single use per cycle  External constraints: -Amount of hardware available: -Area, units etc. -Timing constraints

7 SoC-MOBINET courseware[M-1] High Level Synthesis7 AFAP scheduling AFAP ( As Fast As Possible ) Basic idea:  Control-flow directed graph - Nodes (ops.). Edges (precedence relations).  Longest path: Max number of operations. Cycles only traversed once (%loop unfolding)  Scheduling: Put as many operations into one control step as possible in all possible paths. Goal: Finite State Machine to implement control

8 SoC-MOBINET courseware[M-1] High Level Synthesis8 AFAP Scheduling for a single path AFAP Sch. for a single path ( no loops/branches ) 1.Longest path is computed 2.For every path constraints are computed (variables, IOs, func. Units, max delay) and “Cut”s are lain in according to constraints 3.Interval graph is formed with cliques (complete subgraph of all poss. edges) 4.Cuts an cliques are stored for later processing

9 SoC-MOBINET courseware[M-1] High Level Synthesis9 AFAP Scheduling for a single path

10 SoC-MOBINET courseware[M-1] High Level Synthesis10 AFAP – The algorithm The four steps to Nirvana ( or something ): 1.Transform the control flow graph into a directed acyclic graph (DAG) 2.All paths in the DAG are scheduled AFAP 3.Schedules are overlapped in a way to minimize the number of control steps 4.The finite state machine is built.

11 SoC-MOBINET courseware[M-1] High Level Synthesis11 AFAP – Example

12 SoC-MOBINET courseware[M-1] High Level Synthesis12 Building finite state machine Trivial finite state machine design:  Overlapping of intervals to form states (same cut -> same state)  Construct state transitions (figure out control signals for each state)  Construct state transition conditions (rules for looping, waiting etc)

13 SoC-MOBINET courseware[M-1] High Level Synthesis13 Results  Comparison is difficult since goals are different.  Different compiler machines used

14 SoC-MOBINET courseware[M-1] High Level Synthesis14 Conclusion: Good things / bad things Good things: Real life examples Good results Bad things: No support for secondary hardware constraints - like busses, registers, ports etc. No smart loop unfolding capabilities No pipeline scheduling capabilities No instruction execution reordering supported


Download ppt "Courseware Path-Based Scheduling Sune Fallgaard Nielsen Informatics and Mathematical Modelling Technical University of Denmark Richard Petersens Plads,"

Similar presentations


Ads by Google