1. Performed by: Lin Ilia Khinich Fanny Instructor: Fiksman Eugene המעבדה למערכות ספרתיות מהירות High Speed Digital Systems Laboratory הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Technion - Israel institute of technology department of Electrical Engineering Characterization Presentation Virtex II Pro FPGA Dynamic Reconfiguration Spring semester 2005

2. Virtex II Pro FPGA Controller reconfiguration System Description

3. Learning of Xilinx Development Environment in application to Virtex II Pro device family. Learning Partial Dynamic Reconfiguration feature of Virtex II Pro device and analysis of its styles for specific applications. Implementation of an Example Application using described feature. Analysis of the Implementation results. Project Goals

4. 4 HW Block Diagram HW Description Synthesize P&R BIT File/ Download Secondary HW Flow SW Flow Chart Create SW Source Compile Simulate ELF File/ Download SW Flow ISE Design Debug (HW and SW) DATA2BRAM EDK HW/SW Flows HW Block Diagram HW Description Synthesize P&R BIT File/ Download Primary HW Flow

5. 5 System usage Partial reconfiguration is useful for: Applications that require the loading of different designs into the same area of the device. The flexibility to change portions of a design without having to either reset or completely reconfigure the entire device.

6. 6 Project Implementations Tools Hardware V2P7 (Virtex II Pro design style) based Evaluation Board by Memec. PC for running designated EDK. Software Xilinx EDK. VHDL IDE.

7. 7 Project Time Table Get familiar with the Xilinx V2P7 board and Virtex II Pro FPGA. Studying Simulation and Synthesis programs (EDK, HDL Designer). Studying the VHDL programming language. Definition of the Example Application. Half Semester Presentation.