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1 09/07/01 PD: Verification Vs. Modification Global Routing Detail Routing Placement Clock Tree Synthesis Power/Ground Stripes, Rings Routing IO Pad Placement.

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Presentation on theme: "1 09/07/01 PD: Verification Vs. Modification Global Routing Detail Routing Placement Clock Tree Synthesis Power/Ground Stripes, Rings Routing IO Pad Placement."— Presentation transcript:

1 1 09/07/01 PD: Verification Vs. Modification Global Routing Detail Routing Placement Clock Tree Synthesis Power/Ground Stripes, Rings Routing IO Pad Placement Layout LayoutVerification estimated accurate Modification easy difficult Extraction and Verification ‘Post’-layout Optimization Not real post-layout optimization, but a new PD loop…

2 2 09/07/01 TEG: A Post-layout Optimization Method Post-layout Optimization Detail Routing Extraction & Verification GeometryLayout TopologicalLayout Topological DRC DRV Solver Layout Modification geometry transform topology extraction layout problems layout operations remove DRVS TEG To be appeared in ISPD’02

3 3 09/07/01 Wire Sizing by TEG Original Layout (LEF/DEF) After wire sizing (LEF/DEF) Fix crosstalk-delay, reduce IR-drop …

4 4 09/07/01 Wire Distribution by TEG Decrease CMP process variation, improve yield and manufacturability… Original Layout After wire distribution

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