1. 11/03/05ELEC 5970-001/6970-001 Lecture 181 ELEC 5970-001/6970-001(Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits Power Consumption in a Memory Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University http://www.eng.auburn.edu/~vagrawal vagrawal@eng.auburn.edu

2. 11/03/05ELEC 5970-001/6970-001 Lecture 182 Intuitive Architecture Word 0 Word 1 Word 2 M bits Storage cell Word N-2 Word N-1 Input-Output (M bits) N words S0S0 S N-1

3. 11/03/05ELEC 5970-001/6970-001 Lecture 183 Memory Organization Sense amplifiers/drivers Column decoder A K A K-1 A L-1 Storage cell Word line Bit line Input-Output (M bits) A 0 A K-1 2 L-K M.2 K

4. 11/03/05ELEC 5970-001/6970-001 Lecture 184 Cell Array Power Management Smaller transistors Low supply voltage Lower voltage swing (0.1V – 0.3V for SRAM) –Sense amplifier restores the full voltage swing for outside use.

5. 11/03/05ELEC 5970-001/6970-001 Lecture 185 Sense Amplifier bit SE Sense ampl. enable: Low when bit lines are precharged and equalized VDD Full voltage swing output

6. 11/03/05ELEC 5970-001/6970-001 Lecture 186 SRAM Cell bit VDD Sense amplifier PC EQ Output BL WL Precharge circuit

7. 11/03/05ELEC 5970-001/6970-001 Lecture 187 Hierarchical Organization Global data bus Global amplifier/driver I/O Block 0 Block 1 Block P-1 Control circuitry Block selector Row addr. Column addr. Block addr.

8. 11/03/05ELEC 5970-001/6970-001 Lecture 188 Power Saving Block-oriented memory –Lengths of local word and bit lines are kept small. –Block address is used to activate the addressed block. –Unaddressed blocks are put in power-saving mode; sense amplifier and row/column decoders are disabled. Power is maintained for data retention.

9. 11/03/05ELEC 5970-001/6970-001 Lecture 189 Static Power 0.00.61.21.8 Supply voltage 1.3μ 1.1μ 900n 700n 500n 300n 100n 0.13μ CMOS 0.18μ CMOS 8-kbit SRAM 7x increase Leakage current (Amperes)

10. 11/03/05ELEC 5970-001/6970-001 Lecture 1810 Adding Resistance in Leakage Path SRAM cell array SRAM cell array SRAM cell array GND VDD sleep Low-threshold transistor VSS.int VDD.int

11. 11/03/05ELEC 5970-001/6970-001 Lecture 1811 Lowering Supply Voltage SRAM cell array SRAM cell array SRAM cell array GND VDD sleep VDDL= 100mV for 0.13μ CMOS Sleep = 1, data retention mode

12. 11/03/05ELEC 5970-001/6970-001 Lecture 1812 References K. Itoh, VLSI Memory Chip Design, Springer-Verlag, 2001. J. M. Rabaey, A. Chandrakasan and B. Nikolić, Digital Integrated Circuits, Upper Saddle River, New Jersey: Pearson Education, Inc., 2003.