1. NACK Digital Equalizer Nguyen Craig Petersen Andrew Nguyen Kevin Wong Group 7 CPSC 483 - 502 © 2000 Midterm Proposal

2. Problems Encountered State Machine Transitions Much Too Fast - Solved by Decreasing Clock (LED Circuit) Difficult to Test LED (Column) Display Without Proper Band Filtering NS16550 UART (Communications IC) Becomes Extremely Hot Serial Communication More Difficult to Implement than Previously Expected

3. Modifications? Added LED (Digital) Display For Easy Reference (dB levels) 5-Bands Used Instead of 7-Bands Not 7-Band Due to National Semiconductor IC Becoming Obsolete dB Range in Increments of 2.4 (-12 to +12) Instead of +1/-1 dB (Due to IC Used)

4. Modifications (Cont.) Software/Hardware = 65% - 35% (Now) Software/Hardware = 35% - 65% (Previous) Transition due to FPGA Implementation and Not TTL

5. Results/Partial Results Obtained LED (Digital) Display Counting from -12 to +12 (dB) in 2.4 Increments - 10 Steps LED (Column) Works but Unable to Test Individual Bands 5-Band Equalizer Semi-Communicates with UART (Output Response Undetermined)

6. Results/Partial Results Obtained (Cont.) UART Can Transmit/Receive Data When Test By Switching Wire Manually Internal Baud Generator of UART Can Be Programmed By State Machine A Functional Stand Alone FPGA

7. Assignment of Responsibilities - Updated Nguyen - Software Program, UART FPGA Control Andrew - Testing Equalizer Craig - Interfacing LCD, Constructing LED (Digital) Display, LED Column Display, Assisting Andrew with Equalizer Circuit Communication Kevin - Serial Interface, Software Program, UART FPGA Control, Stand Alone FPGA

8. Levels Encountered - (1 = Best 4 = Very Poor) Difficulties Faced Implementing Project - 2 Serial Interface Being Problematic Coordination Among Team Members (Availability) - 3 Everyone is interviewing and busy with classes Support From the Lab - 1 Lab TA is extremely helpful

9. 5-Band Equalizer Specs Monolithic integrated 5-band stereo equalizer circuit Five filters for each channel Center frequency, bandwidth and maximum boost/cut defined by external components

10. 5-Band Equalizer Specs (Cont.) Choice for variable or constant Q-factor via I^2 C software The 5-band stereo equalizer is an I^2 C- bus controlled tone Processor for application in car radio sets, TV sets and Music centers.

11. 5-Band Equalizer Specs (Cont.)  Defeat mode  All stages are DC-coupled  I^2 C-bus control for all functions  Two different module addresses programmable.

12. Andrew Nguyen’s Contributions Fabricate the Hardware Build State Machine for the Equalizer Build the Circuit for the Equalizer Test the Equalizer Help Craig and Kevin

13. Craig Petersen’s Contribution Developed Both a Hardware and FPGA Version of LED (Digital) Display (State Machine) - Displays Band, dB Level, Positive/Negative Sign, and decimal point Developed LED (Column) Display Using 10 LEDs for Each Band Helping Andrew Communicate with Equalizer Circuit - State Machine and Verilog Code for I 2 C Bus

14. Kevin Wong’s Contribution Worked On Equalizer Control Software (PC - Visual Basic) Wired-Up Stand-Alone FPGA Built The Serial Interface Circuit Implemented UART Control State Machine Also helped Andrew and Craig

15. Nguyen Nguyen’s Contributions Write code in Visual Basic to test on a loop- back cable. Help around in making circuit board layout. Figure out the pin number on Xilinx chip to connect to RS-232. Using state machine to change the state of output frequencies.

17. RS-232 Logic VS. TTL Logic

18. Serial Interface Schematic MAX 232 16550 UART FPGA DATA (D0..D7) ADDRESS (A0..A2) READ WRITE Rx Tx Rx Tx Other Control/Equalizer Component Serial Port (PC Connection)

19. FLOW DIAGRAM

20. UART Control State Machine Initialize UART: Serial Characteristics Band Generator FIFO/16450 Mode IN OUT Din[7:0] Dout[7:0] MEMin[7:0] MEMout[7:0]WRRD RxRDYTxRDY A[2:0] START Wait For Data To Transmit/Receive Transmit: Put Data From MEMin to Dout For UART to Transmit Receive: Get Data From Din to MEMout For FPGA TxRDY RxRDY

21. MAX-232 Driver/Receiver 2 Receivers & 2 Transmitters Generates +10V & -10V From Single 5V

22. RS-232 Data Format HIGH LOW Idle 5-to-8 Data Bits Parity Bit Stop Bit Idle Start Bit D0DnPStSr Period = 1 / Frequency Frequency = 16 * Baud Rate Ex: 115200bps => Frequency = 16 * 115200 = 1.8432MHz

23. Universal Asynchronous Receiver/Transmitter Serial-to-Parallel / Parallel-to-Serial Conversion 16 Bytes Receive/Transmit Storage Buffer Add/Delete Standard Asynchronous Communication Bits Build-in Programmable Baud Generator 16550 UART

24. UART Settings 8 Data Bits, 1 Stop Bit, No Parity Bit 115200bps Baud Rate 18.432MHz Clock (Baud Rate Divisor: 10)

25. Week-by-Week Goals

27. List of Components for implementation Graphic driver program to digitally control the equalizer’s activities A workstation/pc for the software package A soundcard A bus interface 7 analog filters and gain system 14 operational amplifier Resistors Capacitors

28. List of Components for implementation (cont ….) Switches/selectors LEDs display bar Decoders/Demuxes Diodes LCD display Xilinx tool/Labview

29. List of Components for testing 1. Breadboard 2. Oscilloscope 3. Function Generator 4. Digital Multimeter

30. List of special testing environments Xilinx circuit board PC with available COM port and sound card Audio speakers Music files Oscilloscope

31. Percentage of software and hardware work involved Hardware: 60 - 65% Software: 35 - 40%

32. Cost of prototype

33. Technical Specifications

34. Team Assignments