1. Idongesit Ebong (1-1) Jenna Fu (1-2) Bowei Gai (1-3) Syed Hussain (1-4) Jonathan Lee (1-5) Design Manager: Myron Kwai Overall Project Objective: Design a chip as part of a system that accommodates the growing demand for radio frequency identification (RFID) technology while creating a quicker, more convenient shopping experience. Presentation #7: Smart Cart 525 Stage VII: 28 Feb. 2005 Functional Block Layout and Floorplan

2. Status Design Proposal Project chosen Verilog obtained/modified Architecture Proposal Behavioral Verilog simulated Size estimates/floorplanning Gate-level implementation simulated in Verilog Floorplan and more accurate transistor count Schematic Design Component Layout Functional Block Layout (still working on encryption) DRC of functional blocks LVS of functional blocks  Simulations

3. Design Decisions Modification to floorplan  Some components smaller than expected  Moved 32-bit mux/buffer/reg/buffer from encryption block to main block; needed to make encryption skinnier and main fatter  Moved SRAM to top, adder to bottom, and registers on top of SRAM  Using row decoder of SRAM as routing channel for 20-bit input and 14-bit output bus

4. Design Decisions Decided on modified master-slave DFF for input/output registers  Don’t have to gate clk this way  Plan to use regular master-slave for other registers in the design

5. Updated Transistor Count OldNew Encryption13,054 Multiplier36622042 Adder902544 SRAM2276 Logic1000400 Registers (inputs/outputs, counters)15402540 Total22,43420,856

6. Updated Floorplan Estimated Area:Old (μm 2 )New (μm 2 ) Encryption68,352 Multiplier12,7208856 Adder23123920 SRAM963910,695 Logic/Wiring10,72114,655 Registers (inputs/outputs, counters)80004490 Total111,744110,968 Estimated density: ( transistors/μm 2 ).2.19

7. Old Floorplan: Entire Design

8. New Floorplan: Entire Design v SRAM Input Registers Adder v Multiplier

9. Floorplan: Fitting everything together Registers A closer look

10. Floorplan: Global wiring done on individual blocks

11. Floorplan: Global wiring end result

12. Layout: Encryption (Small ROM)

13. Layout: Encryption (Mix Column)

14. Layout: Encryption (SBOX)

15. Layout: Multiplier

16. Layout: Carry-Select Adder

17. Layout: Register (Old)

18. Layout: Register (New) To be used for input/output registers

19. Layout: Register To be used elsewhere in the design (counters, etc.)

20. Problems & Questions Simulations for Adder/Multiplier: ran, but weren’t good  XOR implementation of FA led to some signal strength problems in simulations  Need to add buffers, which will possibly fill up some extra space left by initial layout Wiring in encryption block