1. Configuration of FPGAs Using (JTAG) Boundary Scan Chen Shalom www.cs.huji.ac.il/~chensha

2. Agenda FPGAs - overview Using FPGA – from HDL to chip FPGA configuration Using JTAG Summary

3. F ield P rogrammable G ate A rray What are FPGAs ? Who makes FPGAs ? FPGA vs. CPLD Internal logic - overview

4. What are FPGAs ? FPGAs are programmable digital logic chips Can be programmed to almost any digital function FPGA can be configured many times with different functions If we have bug in our design- we fix it in the RTL and configure the FPGA again FPGAs are much faster than a design board with discrete components FPGAs are volatile devices

5. Who makes FPGAs ? Xilinx – Virtex, VirtexII, VirtexII-pro Altera Lattice Actel Quicklogic

7. FPGAs vs. CPLDs FPGAsCPLDs “fine-grain”“coarse-grain” RAM based- need to be downloaded at each power up EEPROM based- active at power up SlowerFaster Can hold very large designs Can contain small designs only

8. Internal Logic Thousands of Basic logic cells Each logic cell consist: Small lookup table Some basic gates D-flipflop Logic cells can be connected using interconnect resources (wires/muxes)

9. Using FPGA From HDL to chip

10. Using FPGA netlist place & route config Write synthesizable RTL in HDL Create the netlist from a HDL code Place and route according to the module constrains – creating a binary file Configure into the FPGA

11. FPGA configuration Using JTAG What does it means ? The JTAG interface Virtex Boundry Scan Instructions Virtex Boundry Scan Registers The configuration sequence

12. What does it means ? Configuring an FPGA means downloading a stream of 0’s and 1’s into it through some special pins The FPGA has 2 states- “configuration mode” and “user mode” Once the FPGA is configured, it goes into “user mode” and becomes active A special PROM on board configures the FPGA automatically at power-up

13. The JTAG interface Standard JTAG commands can be used to take control of each pin in the chain In addition to testing, BS offers a device to have it’s own set of user defined instructions The added instructions, such as configure and verify, have increased the popularity of BS devices BS FPGAs has the ability to be configured through the BS chain

14. Virtex Boundry Scan Instructions

15. Virtex Boundry Scan Registers The Virtex family is fully compliant with BS.1 In addition it supports some optional registers:

16. The configuration sequence Power up – FPGA in configuration mode Get INIT==1 Load CFG_IN instruction Load bitstream from the BSR Load JSTART instruction Start up sequence The FPGA is operational !!

17. An example for binary code 0011 0000 0000 0001 0010 0000 0000 0001 -> Header: Write to COR 0000 0000 1010 0000 0011 1111 1111 1111 -> COR data sets SHUTDOWN = 0 0011 0000 0000 0000 1000 0000 0000 0001 -> Header: Write to CMD 0000 0000 0000 0000 0000 0000 0000 0101 -> Header: Start command 0011 0000 0000 0000 1000 0000 0000 0001 -> Write to CMD 0000 0000 0000 0000 0000 0000 0000 0111 -> RCRC command 0000 0000 0000 0000 -> flush pipe

18. Xilinx Virtex FPGA

19. A JTAG cable Connects between the PC to the FPGA board

20. The Ximpact tool

21. Summary

22. Az ma haya lanu sham ?? FPGA is a programmable chip The best friend of the HW designer Built with many basic cells JTAG is a great interface for FPGAs configuration- added instructions and regs The configuration sequence Future – IEEE 1532 Element

23. BGU Pictures

24. Board infrastructure

25. The BGU device

26. The warm-air machine