1. High-level System Modeling and Power Management Techniques Jinfeng Liu Dept. of ECE, UC Irvine Sep. 2000

2. Background  X2000 Avionics System Architecture  COTS – based building blocks for system integration  Low cost component with strong commercial support  Widely accepted specification, design, application and testing  Reduced development cost  Dual system bus architecture  IEEE 1394 bus  Hi performance on fast data rate  Moderate power  Reconfigurable structure  I 2 C bus  Low power  Adequate data rate for low-speed communication

3. Examples  X2000 Power Requirement  Computing performance  10 – 20 times increase  Power consumption  10 times decrease in digital electronics  2 times decrease in analog electronics  Mars Rover Power management  Mission requirement  Image and scientific experiment  Power supply  Non-rechargeable battery and solar panel  Power management solution  Serialize all operations to avoid exceeding power supply margin

4. What is PACC?  Low power design – as low as possible  Minimize power consumption at circuit/gate level  No system-level and application specific knowledge  Limited reconfiguration space to meet multiple mission requirement  Power aware computation – use power wisely  Power model built on application-specific knowledge  Reconfigurable system architecture to meet multiple mission requirement  Adaptive adjustment to run-time power supply  Optimize power usage on system level  Use power efficiently to complete computation  Regulate power surge to protect battery  Shorten execution time to save energy

5. Our Approach  High-level system modeling techniques  Describe the system in high-level abstractions  Employ application specific knowledge in system models  Apply power aware management methodologies in different levels  System models  Behavioral modeling – software architecture, application specific knowledge  Architectural modeling – hardware platform  Partitioning – mapping behavioral objects to architectural structures  Scheduling – a valid sequence of concurrent/parallel operations on multiple processors that satisfies real-time requirement

6. Our Approach  Power management and optimization  Behavioral modeling – extract power related attributes of all objects  Architecture modeling – use low-power devices or devices that can operate on low-power mode  Partitioning – merge computations on under-utilized processors on one processor to improve utilization  Partitioning – separate tightly coupled computations into clusters to localize communication  Scheduling – arrange operation sequence to satisfy power apply limitation and regulate power consumption within a stable range

7. Behavioral Model  Application specific knowledge  Input, output and function  Dependency and precedence  Control and data flow  Timing and sequence  Software architecture  Operating system features – real-time, centralized, distributed, and etc.  Execution model – event driven, interrupt, distributed agent, client-server, and etc.  Communication model – protocol stack and specification  Power related attributes  Data rate, execution time, CPU speed, memory size, communication path, and etc.

8. Architectural Model  Component – available COTS  Type – processor, memory, I/O, DSP, bus, and etc.  Interface – how the components can be connected to each other  Modes – operation modes parameters, voltage, clock speed, bandwidth, power consumption, and etc.  Package – a bundle of connected components that performs certain operation  Components – a set of connected components  Internal/external interface – how components are connected  Modes – configuration space of the collected components specified by each component’s working mode and collective attributes, e.g., voltage, speed, power and etc.

9. Partitioning  Mapping – map behavioral objects to hardware  Group related OS, communication, control and application objects into processing nodes  Extract data objects into storage nodes  Allocate components/packages for each processing node  Arrange data storage for data nodes and optimize storage location to reduce communication  Establish communication paths among nodes that comply with the communication model  Setup working mode of each component/package to fit the behavioral requirement  Extract attribute of each structure  Function – computation, control, communication  CPU utilization  Bus traffic  Power consumption

10. Partitioning  Migration – combine multiple nodes to one node to improve utilization  Examine the utilization of each processor  Migrate computation on under-utilized processors and merge corresponding storage if necessary  Balance power consumption and CPU utilization  Segmentation – arrange nodes in tight communication in a bus segmentation  Group nodes by communication localities  Settle each group in a bus segment (a feature of IEEE 1394)  Extract attributes of localized communication mode in a segmented bus  Improved performance  Reduced bus traffic  Reduced power consumption

11. Scheduling  Scheduling techniques  Deadline based real-time scheduling on multiprocessors  Rate-monotonic scheduling – extend existing RM scheduling to multiprocessors  Timing constraint graph scheduling – multiple serializable sequences in single heart beat  Constraint logic solving  Transfer all constraints into a pure mathematical form  Use tools to solve the problem in mathematical domain  Power constraint scheduling  Schedule events to meet power requirement  Regulate power surge  Use power efficiently to reduce execution time  Use graphic tool to visualize power consumption

12. Scheduling  Our scheduling tool  A novel graphical tool that visualize timing and power constraint and transforms them into simple graph problems  Event – bins  Timing – horizontal size  Power – vertical size  Energy – area of the bin  Power surge – compacting bins downward  Timing constraints – bin packing problem to satisfy horizontal constraints  Power constraints – bin packing problem to satisfy vertical constraints  Powerful management and optimization tool to give designers a vision to the power surge on run-time

13. Power Scheduling Graph A BBBB CCCC C DDD Constant task A Periodic task B Periodic task C Task D follows B Processor 1 Processor 2 Power Time Extended Gantt chart to describe parallel operations on multiprocessors with power consumption attributes Starting time Ending time Power levelEnergy consumption

14. Timing Constraint A B C D Power Time B C Deadline of B (scheduling space) Deadline of B Min timing constraint of D Max timing constraint of D Deadline of C (scheduling space) Deadline of C Timing constraints defined by deadline, min and max timing constraint limit the horizontal position of each bin Scheduling space of D

15. Power Constraint Time A BBBB C C C C C D D D Power CDCC A BBBB CCCC C DDD Time Max power Compacting bin downward makes the curve of power surge Max power

16. Scheduling A B C D Power Time B C Deadline of B Min timing constraint of D Max timing constraint of D Deadline of C C D Slide bin within timing space to meet power constraint C Squeeze/extend bin to available time slot to meet power constraint. This may require changing clock speed of the processor, and power consumption should be also changed. Scheduling becomes a bin-packing problem

17. How it works Time A BBBB C C C C C D D D Power CDCC Max power Designers can slide the bins on timing constraint graph while monitoring power surge on power constraint graph Min power A BBBB CCCC C DDD Power Time Power constraint graph Timing constraint graph

18. Examples  Mars Rover Power Management – walking mode  System specifications  Six driving motors for wheels  Four steering motors  Heaters for each motor  System health check  Hazard detection  Timing constraints  Power constraints  Solutions  Serialize each operation to satisfy power constraint  Too conservative usage of power  No scheduling tool is used

19. Scheduling Results  To be continued  Under construction