1. ENGN3213: Digital Systems and Microprocessors L#8 1 Lecture 8 Overview Review of Combinational Logic Technologies Logic Implementation Programmable Logic Devices

2. ENGN3213: Digital Systems and Microprocessors L#8 2 Simple gate summary INPUTOUTPUT ABA AND B 000 100 010 111 INPUTOUTPUT ABA NAND B 001 101 011 110 INPUTOUTPUT ABA OR B 000 101 011 111 INPUTOUTPUT ABA NOR B 001 100 010 110

3. ENGN3213: Digital Systems and Microprocessors L#8 3 The XOR gate Exclusive OR The output is TRUE only if one or the other, but not both, inputs are TRUE Symbol is  C C=A XOR B C=A  B ABC (in) (out) 000 011 101 110

4. ENGN3213: Digital Systems and Microprocessors L#8 4 The XNOR gate Inverse of XOR The output is TRUE only if both inputs are the same. "logical equality” C C=A NOR B C=A  B ABC (in) (out) 001 010 100 111

5. ENGN3213: Digital Systems and Microprocessors L#8 5 CMOS gates Gates are very easy to build using MOSFET transistors (recall; transistors can be considered as a voltage controlled switch) p-type conduct when the input=0 n-type conduct when the input=1

6. ENGN3213: Digital Systems and Microprocessors L#8 6 CMOS NAND gate NAND gates are built using 4 MOSFETs p-type conduct when the input=0 n-type conduct when the input=1 INPUTOUTPUT ABA NAND B 001 101 011 110

7. ENGN3213: Digital Systems and Microprocessors L#8 7 Review of Gate Processing A NOT gate inverts its single input An AND gate produces 1 if both input values are 1 An OR gate produces 0 if both input values are 0 An XOR gate produces 0 if input values are the same A NAND gate produces 0 if both inputs are 1 A NOR gate produces a 1 if both inputs are 0

8. ENGN3213: Digital Systems and Microprocessors L#8 8 Can combine gates To make different logic outputs B A out

9. ENGN3213: Digital Systems and Microprocessors L#8 9 Logic Types Positive Logic (active high) – 0 = 0 V., 1 = 1.0 V. Negative Logic (active low) – 0 = 1.0 V., 1 = 0 V. Mixed-Logic – logic with: –Negative (positive) logic inputs –Positive (negative) logic outputs –Arbitrary mixture of positive & negative logic

10. ENGN3213: Digital Systems and Microprocessors L#8 10 INPUTOUTPUT ABA AND B 000 100 010 111 In order for the Output of an AND Logical Function to be TRUE: input A AND input B must both be TRUE. This is Positive Logic. Using the Same Function -It is also correct to say: If either input A OR input B (or both) is NOT TRUE the Output Will be FALSE. This is Negative Logic. Positive vs Negative Logic A B Out

11. ENGN3213: Digital Systems and Microprocessors L#8 11 Multiple Gate Interpretations Positive logic: Negative logic:

12. ENGN3213: Digital Systems and Microprocessors L#8 12 SOP and POS Any logical expression can be reduced to either a "Sum-of-Products" form or a "Product-of-Sums" form

13. ENGN3213: Digital Systems and Microprocessors L#8 13 DeMorgan's Theorem Proof Duality between AND and OR means that any logic function can be implemented by using just OR and NOT gates (NOR), or by just AND and NOT gates (NAND) "break the line, change the sign"

14. ENGN3213: Digital Systems and Microprocessors L#8 14 CMOS NAND gate The NAND gate is by far the most important It is cheapest to construct It can be used to produce all other logic operations

15. ENGN3213: Digital Systems and Microprocessors L#8 15 CMOS NAND gate The NAND gate is by far the most important It is cheapest to construct It can be used to produce all other logic operations XOR

16. ENGN3213: Digital Systems and Microprocessors L#8 16 NAND Gate Implementation De Morgan’s law tells us that is the same as By definition, is the same as  All sum-of-products expressions can be implemented with only NAND gates.

17. ENGN3213: Digital Systems and Microprocessors L#8 17 Use of DeMorgan’s Theorems to Transform Logic Gates

18. ENGN3213: Digital Systems and Microprocessors L#8 18 Choice of Logic Realization CMOS, nMOS, & TTL logic families –Fewer transistors in NAND/NOR gates than in AND/OR gates –NAND/NOR also faster than AND/OR Gate substitution: Use 3-input AND gate instead of cascaded 2-input AND’s (faster)

19. ENGN3213: Digital Systems and Microprocessors L#8 19 Combinational analysis... derives truth table

20. ENGN3213: Digital Systems and Microprocessors L#8 20 Signal expressions F = ((X + Y)  Z) + (X  Y  Z)

21. ENGN3213: Digital Systems and Microprocessors L#8 21 New circuit, same function Multiply out: F = ((X + Y’). Z) + (X’. Y. Z’) = (X. Z) + (Y’. Z) + (X’. Y. Z’)

22. ENGN3213: Digital Systems and Microprocessors L#8 22 F = ((X + Y’)Z) + X’YZ’ Note: [X’YZ’]Z = 0 (X + Y’)X’YZ’ = 0 (X’YZ’)(X’YZ’) = X’YZ’ So, F = [(X + Y’) + X’YZ’][Z + X’YZ’] =(X + Y’ + X’)(X + Y’ + Y)(X + Y’ + Z’)(Z + X’)(Z + Y)(Z + Z’) =(1)(1)(X + Y’ + Z’)(X’ + Z)(Y + Z)(1) = (X + Y’ + Z’)(X’ + Z)(Y + Z) Circuit: Any number of manipulations can yield equivalent circuits e.g.

23. ENGN3213: Digital Systems and Microprocessors L#8 23 Another example: Push bubbles to obtain cancellations

24. ENGN3213: Digital Systems and Microprocessors L#8 24 Another example: Push bubbles to obtain cancellations

25. ENGN3213: Digital Systems and Microprocessors L#8 25 Conclude: given circuit ==> many equivalent equations circuit does not determine equation

26. ENGN3213: Digital Systems and Microprocessors L#8 26 Two-level AND-OR Three-level equivalent Two-level NAND-NAND Also, equation does not determine circuit:

27. ENGN3213: Digital Systems and Microprocessors L#8 27 Combinational analysis given circuit, determine function Combinational synthesis given function, determine circuit

28. ENGN3213: Digital Systems and Microprocessors L#8 28 Design Considerations In addition to logic functions, a designer must be concerned with a number of physical characteristics of digital logic circuits, including the following: –Propagation delays –Gate fan-in and fan-out restrictions –Power consumptions –Size and weight.

29. ENGN3213: Digital Systems and Microprocessors L#8 29 Programmable Arrays of Logic Gates Until now, we learned about designing Boolean functions using discrete logic gates We will now describe a technique to arrange AND and OR gates (or NAND and NOR gates) into a general array structure Specific functions can be programmed Can use programmable logic arrays (PLA) or programmable array logic (PAL)

30. ENGN3213: Digital Systems and Microprocessors L#8 30 Programmable Logic Devices PROM (Programmable Read-only Memory) PLA (Programmable Logic Array) PAL (Programmable Array Logic) FPGA (Field-Programmable Gate Array)

31. ENGN3213: Digital Systems and Microprocessors L#8 31 Programmable Logic Device What is a Programmable Logic Device (PLD)? –an IC that contains large numbers of gates, flip-flops and registers that are interconnected on the chip –can be configured by the user to perform a logic function – less board space – smaller enclosures – faster and less costly assembly processes – higher reliability (fewer ICs and circuit connections => easier troubleshooting)

32. ENGN3213: Digital Systems and Microprocessors L#8 32 Programmable Logic Device Basic Ideas of PLD – A PLD consists of an array of AND gates and an array of OR gates – Each input feeds both a non-inverting buffer and an inverting buffer to produce the true and inverted forms of each variable. (i.e. the input lines to the AND-gate array) – The AND outputs are called the product lines – Each product line is connected to one of the inputs of each OR gate – Three fundamental types of standard PLDs: PROM, PAL, and PLA

33. ENGN3213: Digital Systems and Microprocessors L#8 33 PALs and PLAs Pre-fabricated building block of many AND/OR gates (or NOR, NAND) "Personalized" by making or breaking connections among the gates Programmable Array Block Diagram for Sum of Products Form

34. ENGN3213: Digital Systems and Microprocessors L#8 34 Internal Structures of PLD

35. ENGN3213: Digital Systems and Microprocessors L#8 35 Programmable Read-Only Memory (PROM) Each possible minterm AND gate is present (fixed AND) plane and configurable OR plane Can use it to do address decoding Can also be use to implement logic functions

36. ENGN3213: Digital Systems and Microprocessors L#8 36 Decoders A decoder always has n inputs and 2 n outputs. n bit address for 2 n bit word of memory Given any input to a decoder, only one decoder output is 1. From truth table, circuit for 2x4 decoder Each output is a 2-variable minterm (X'Y', X'Y, XY' or XY) F 0 = X'Y' F 1 = X'Y F 2 = XY' F 3 = XY XY

37. ENGN3213: Digital Systems and Microprocessors L#8 37 Decoders Design a 3x8 decoder. F 1 = x'y'z xzy F 0 = x'y'z' F 2 = x'yz' F 3 = x'yz F 5 = xy'z F 4 = xy'z' F 6 = xyz' F 7 = xyz

38. ENGN3213: Digital Systems and Microprocessors L#8 38 Implementation of ROMs ROM can be implemented using orthogonal arrangement of wires –optional connection at each intersection –decoder puts logic ‘1’ on exactly one of the horizontal wires - this can be detected at output if connection present Some PROMs are configured by breaking connections –high voltage placed across one input and one output at a time –high current flow causes “fuse” at intersection to “blow” Other PROMs can be erased and reprogrammed (EPROMs) stored functions –  m (0,1,3,4,6),  m (0,1,3,5,7),  m (2,3,6,7),  m (0,3,4,6)

39. ENGN3213: Digital Systems and Microprocessors L#8 39 ABCD A B C D A A A A A A A A A A A A A A A F 1 F 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 S 3 S 2 S 1 S 0 4:16 dec Enb F 2 Decoder as a Logic Building Block Example Function: F1 = A' B' C D + A' B C' D + A B C D F2 = A B C' D' + A B CD' + A B C D F3 = (ABC D)'

40. ENGN3213: Digital Systems and Microprocessors L#8 40 Programmable Logic Arrays PLAs have configurable “AND-plane” & “OR-plane” Can implement any 2-level AND-OR circuit Efficient physical implementation in CMOS x0x0 x1x1 x2x2 x3x3 x4x4 x5x5 z0z0 z1z1 z2z2 z 3 = x 0 x 1 x 2 x 3 x 4 x 5 + x 0 x 1 x 2 x 5 x 0 x 2 x 3 x 4 x 5 x 0 x 1 x 2 x 3 x 4 x 5 x 0 x 2 x 4 x 5 x 0 x 1 x 2 x 5 x 0 x 4 x 5 x 1 x 2 x 3 x 4 configurable connection

41. ENGN3213: Digital Systems and Microprocessors L#8 41 Programmable Array Logic (Limited PLA) PAL is similar to PLA but fixed OR-plane Simpler to program and cheaper implementation Limited number of terms in each output x0x0 x1x1 x2x2 x3x3 x4x4 x5x5 z0z0 z1z1 z 2 = x 0 x 2 x 3 x 4 x 5 + x 0 x 1 x 2 x 3 x 4 x 5 x 0 x 2 x 3 x 4 x 5 x 0 x 1 x 2 x 3 x 4 x 5 x 0 x 2 x 4 x 5 x 0 x 1 x 2 x 5 x 0 x 4 x 5 x 1 x 2 x 3 x 4 configurable connection

42. ENGN3213: Digital Systems and Microprocessors L#8 42 Alternative Representations Short-hand notation so we don't have to draw all the wires! Notation for implementing F0 = A B + A' B' F1 = C D' + C' D F0 F1F2F3 ABCD

43. ENGN3213: Digital Systems and Microprocessors L#8 43 Field Programmable Gate Arrays FPGA roots are in the CPLDs of the 1980's Invented by Ross Freeman (co-founder of Xilinx) in 1984. FPGAs can be used to construct more complex circuits Applications of FPGAs include DSP, aerospace, defense systems, computer vision, speech recognition, cryptography etc. FPGAs especially find applications in any area or algorithm that can make use of the massive parallelism offered by their architecture. Chip contains a large number (1,000s to 100,000s) of configurable building blocks CAD tools map high level circuit to basic blocks, configuring function generators & other configurable elements as needed

44. ENGN3213: Digital Systems and Microprocessors L#8 44 FPGA An FPGA contains both logic blocks and programmable routing (interconnects) A logic block is a circuit block that is replicated in an array in an FPD A logic block consists of clusters of logic cells Each logic cell contains a Look up table (LUT). –They are called Configurable Logic Blocks (CLB) by Xilinx. –based on Look-Up Tables. Most commercial FPGAs have 4-input LUTs –The logic blocks of most SRAM-based FPGAs consist of logic cells –A logic cell consists of a LUT, a flip flop, and connection to adjacent cells. –A logic slice consists of 2 logic cells. –Xilinx counts closer to 2.25 logic cells per slice because they can do more per configurable logic block (CLB) than other architectures

45. ENGN3213: Digital Systems and Microprocessors L#8 45 Xilinx FPGA Organization CLBs can be connected to passing wires Direct lines (DL) allow signal between adjacent CLB DL can be programmed to connect to long wire segments Long wire segments used to connect distant CLBs Wire segments connected by switch matrix Configuration information stored in SRAM bits that are loaded when power turns on switch matrix wire segments configurable logic blocks (CLB) IO blocks (IOB)

46. ENGN3213: Digital Systems and Microprocessors L#8 46 Configuring Logic Lookup table implements logic functions Multiplexors and pass transistors implement routing Switch matrix contains configurable clusters of pass transistors –provides wide variety of routing options f(A,B,C) 0 0 1 0 1 1 1 0 0123456701234567 ABCABC 01230123 01 1 configuration memory

47. ENGN3213: Digital Systems and Microprocessors L#8 47 S/R C D > ECCLR PRE LUT4 LUT3 LUT4 D > ECCLR PRE 1 1 S/R C YQ XQ Y X CLKEC G1 G2 G3 G4 F1 F2 F3 F4 H1 DIN S/R Flip Flop Xilinx Configurable Logic Block Main Function Generators Set/Reset Control Clock Enable Control Clock Edge Select

48. ENGN3213: Digital Systems and Microprocessors L#8 48 Things You Should Know ROMS –Each possible minterm AND gate is present (fixed AND) plane and configurable OR plane –how large a ROM is needed for given set of logic equations? PLAs –Limited number of AND gates –Programmable AND and OR gates. PALs –Programmable AND plane –how are logic functions represented? FPGAs –components of FPGA and how they relate to each other –components of typical logic cell (Configurable Logic Block) –how circuits can be mapped onto CLBs