1. E-Voting Machine - Design Presentation Group M1 Bohyun Jessica Kim Jonathan Chiang Chi Ho Yoon Donald Cober Mon, Nov 17 ExtractedRC simulation More Layout Secure Electronic Voting Terminal

2. Data Bus Machine Init FSM User ID FSM Selectio n FSM Confirm ation FSM Display User ID SRAM Message ROM Card Reader Fingerprint Scanner Encryption Key SRAM User Input Write-in SRAM Choice SRAM TX_Check Selection Counter Key Register XOR 8 bit Full Adder 8 bit Full Adder 8 bit Full Adder 8 bit Full Adder XOR 8 bit MUX 01 01 01 16 bit Add/Sub 01 8 bit MUX 16bi t REG 8-bit REG COMMS Register Shift Registe r In Shift Registe r Out constant init

3. COMMS Extracted RC Simulations functioning Buffering added to fix glitches

5. Unbuffered Simulation

6. Buffered Simulation

10. FSM Extraceted RC simulations work 33% of the layout still needs to be cleaned up

11. FSM Layout

12. FSM Encoder Layout

13. Set/ Reset Flip Flop

14. 6 state encoder

15. 10 state encoder

16. 12 state encoder

17. 2 Bit Counter

18. Extended Counters

19. D Flip Flop Layout

20. “!J” Toggle / Reset flip flop

21. 2bit CounterLayout

22. 6bit Counter Layout

23. FSM Simulation (extractedRC)

25. SRAM Row decoders: Complete and LVSing SRAM layout: Complete and LVSing ExtractedRC Simulation In Progress Next time: More Simulation for ExtractedRC

26. 6 bitDecoder ExtractedRC Rise Time

27. 6 bit Decoder ExtractedRC Fall Time

28. SRAM Cell Write ExtratedRC Simulation

29. SRAM Cell Write ExtratedRC Rise Time

30. SRAM Cell Write ExtratedRC Fall Time

31. SRAM Plus 2 bit Decoder with Tristate Buffers Area: 48.74 by 17.15 Transistor: 306 Density: 0.366

32. SRAM Plus 3 bit Decoder with Tristate Buffers Area: 50.94 by 22.86 Transistor: 518 Density: 0.445

33. Extra Blocks Selection counter finished an simulated

34. Selection Counter

35. Seleection Counter Simulation

36. TODO: Merge Our Cadence Directories Finish Layout cleanup Layout: User Input, Key Register, Message ROM Global Inter connects Simulations