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© Dr. Alaaeldin Amin 1 Hardware Modeling & Synthesis Using VHDL Very High Speed Integrated Circuits Start Of VHDL Development 1981 1985 First Publication.

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Presentation on theme: "© Dr. Alaaeldin Amin 1 Hardware Modeling & Synthesis Using VHDL Very High Speed Integrated Circuits Start Of VHDL Development 1981 1985 First Publication."— Presentation transcript:

1 © Dr. Alaaeldin Amin 1 Hardware Modeling & Synthesis Using VHDL Very High Speed Integrated Circuits Start Of VHDL Development 1981 1985 First Publication (Base-Line) 1987 1993 First Publication Of VHDL Standard Publication Of Revised VHDL Standard VHDL = VHSIC Hardware Description Language

2 © Dr. Alaaeldin Amin 2 Background OBJECTIVES: Provide a Standard Medium For –Design Modeling –Design Documentation VHDL is an IEEE Standard (Language Standard) –IEEE VHDL-87 –IEEE VHDL-93 VHDL-93 is Upward Compatible with the VHDL-87 (Minor Differences May Require Code Modification) Requires Simulation and Synthesis Tools By The End of 1995, Most Simulation Tools Have Incorporated Support for the VHDL-93 VHDL Is Also Used For Design Synthesis

3 © Dr. Alaaeldin Amin 3 VHDL Advantages Modular Hierarchical, Allows Design Description : –TOP - DOWN, –BOTTOM - UP, Portable Can Describe the Same Design Entity using More than one View (Domain): –The Behavioral View ( e.g. as an algorithm, Register- Transfer (Data Flow), Input-Output Relations, etc) –The Structural View. This Allows Investigation of Design Alternatives of the Same Entity It Also Allows Delayed Detailed Implementations. Can Model Systms at Various Levels of Abstraction (System, chip RTL, Logic (Gate)) VHDL Can be Made to Simulate Timing At Reasonable Accuracy.

4 © Dr. Alaaeldin Amin 4 VHDL synthesis

5 © Dr. Alaaeldin Amin 5 Hardware MOdeling using vhdl VHDL is NOT CaSe-SeNsItIvE, Thus: Begin = begin = beGiN Semicolon “ ; ” Terminates Declarations or Statements. Line Feeds and Carriage Returns are not Significant in VHDL. DESIGN ENTITY Interface Specs Name Ports (In, Out, InOut) Attributes ICON Architectural Specs Behavioral (Algorithmic, DataFlow) Structural A B Z Name Basic Modeling Unit

6 © Dr. Alaaeldin Amin 6 Example “Ones Count CIRCUIT” Value of C1 C0 = No. of Ones in the Inputs A2, A1, and A0 C1 is the Majority Function (=1 IFF Two or More Inputs =1) C0 is a 3-Bit Odd-Parity Function (OPAR3)) C1 = A1 A0 + A2 A0 + A2 A1 C0 = A2 A1’ A0’ + A2’ A1’ A0 + A2 A1 A0 + A2’ A1 A0’ A0 A2 C0 A1 C1 ONES_CNT C1 Majority Fun C0 Function AND2AND3OR3 OR4

7 © Dr. Alaaeldin Amin 7 Example “Ones Count CIRCUIT INTERFACE SPecs entity ONES_CNT is port ( A : in BIT_VECTOR(2 downto 0); C : out BIT_VECTOR(1 downto 0)); -- Function Documentation of ONES_CNT -- (Truth Table Form) -- --------------------------------------------------- -- This is a COMMENT -- ___________________ -- | A2 A1 A0 | C1 C0 | -- |----------------|------------| -- | 0 0 0 | 0 0 | -- | 0 0 1 | 0 1 | -- | 0 1 0 | 0 1 | -- | 0 1 1 | 1 0 | -- | 1 0 0 | 0 1 | -- | 1 0 1 | 1 0 | -- | 1 1 0 | 1 0 | -- | 1 1 1 | 1 1 | -- |__________ |________| -- end ONES_CNT; 1 2 3 DOCUMENTATIONDOCUMENTATION

8 © Dr. Alaaeldin Amin 8 example “Ones Count CIRCUIT Architectural Body ((((( Behavioral view-1 ))))) architecture Algorithmic of ONES_CNT is begin Process(A) -- Sensitivity List Contains only Vector A Variable num: INTEGER range 0 to 3; begin num :=0; For i in 0 to 2 Loop IF A(i) = '1' then num := num+1; end if; end Loop; -- -- Transfer "num" Variable Value to a SIGNAL -- CASE num is WHEN 0 => C <= "00"; WHEN 1 => C <= "01"; WHEN 2 => C <= "10"; WHEN 3 => C <= "11"; end CASE; -- end process; end Algorithmic;

9 © Dr. Alaaeldin Amin 9 example “Ones Count CIRCUIT Architectural Body ( Behavioral (Data Flow) view - 2 ) architecture Two_Level of ONES_CNT is begin C(1) <=(A(1) and A(0)) or (A(2) and A(0)) or (A(2) and A(1)); -- C(0) <= (A(2) and not A(1) and not A(0)) or (not A(2) and not A(1) and A(0)) or (A(2) and A(1) and A(0)) or (not A(2) and A(1) and not A(0)); end Two_Level; C1 = A1 A0 + A2 A0 + A2 A1 C0 = A2 A1’ A0’ + A2’ A1’ A0 + A2 A1 A0 + A2’ A1 A0’

10 © Dr. Alaaeldin Amin 10 architecture Macro of ONES_CNT is begin C(1) <= MAJ3(A); -- C(0) <= OPAR3(A); end Macro ; Example “Ones Count CIRCUIT Architectural Body ( Behavioral (Data Flow) view - 3 ) Using Functions Functions OPAR3 and MAJ3 Must Have Been Declared and Defined Previously

11 © Dr. Alaaeldin Amin 11 example “Ones Count CIRCUIT Architectural Body ((((( Behavioral view -4 ))))) architecture Truth_Table of ONES_CNT is begin -- Process(A) -- Sensitivity List Contains only Vector A Variable num: BIT_VECTOR(2 downto 0); begin num :=A; CASE num is WHEN "000" => C <= "00"; WHEN "001" => C <= "01"; WHEN "010" => C <= "01"; WHEN "011" => C <= "10"; WHEN "100" => C <= "01"; WHEN "101" => C <= "10"; WHEN "110" => C <= "10"; WHEN "111" => C <= "11"; end CASE; -- end process; end Truth_Table;

12 © Dr. Alaaeldin Amin 12 “Ones Count CIRCUIT example ” C1 = A1 A0 + A2 A0 + A2 A1 =MAJ3(A) C0 = A2 A1’ A0’ + A2’ A1’ A0 + A2 A1 A0 + A2’ A1 A0’ = OPAR3(A) ONES_CNT C1 Majority Fun C0 Odd-Parity Fun AND2AND3OR3OR4 VHDL STRUCTURAL DESCRIPTION entity MAJ3 is PORT( X: in BIT_Vector(2 downto 0); Z: out BIT); end MAJ3; Structural Design Hierarchy entity OPAR3 is PORT( X: in BIT_Vector(2 downto 0); Z: out BIT); end OPAR3;

13 © Dr. Alaaeldin Amin 13 VHDL STRUCTURAL DESCRIPTION Maj3 Majority Function architecture Structural of MAJ3 is COMPONENT AND2 PORT( I1, I2: in BIT; Declare Components O: out BIT); To Be Instantiated END COMPONENT; COMPONENT OR3 PORT( I1, I2, I3: in BIT; O: out BIT); END COMPONENT; -- SIGNAL A1, A2, A3: BIT; Declare Maj3 Local Signals begin -- Instantiate Gates g1: AND2 PORT MAP (X(0), X(1), A1); g2: AND2 PORT MAP (X(0), X(2), A2); Wiring of g3: AND2 PORT MAP (X(1), X(2), A3); Maj3 g4: OR3 PORT MAP (A1, A2, A3, Z); Compts. end Structural;

14 © Dr. Alaaeldin Amin 14 entity OPAR3 is PORT( X: in BIT_Vector(2 downto 0); Interface Specs Z: out BIT); end OPAR3; -- architecture Structural of OPAR3 is COMPONENT INV PORT(Ipt: in BIT; Opt: out BIT); END COMPONENT; COMPONENT NAND3 PORT( I1, I2, I3: in BIT; O: out BIT); END COMPONENT; COMPONENT NAND4 PORT( I1, I2, I3, I4: in BIT; O: out BIT); END COMPONENT; -- SIGNAL A1B, A2B, A0B, Z1, Z2, Z3, Z4: BIT; Architecture beginBody -- Instantiate Gates g1: INV PORT MAP (X(0), A0B); g2: INV PORT MAP (X(1), A1B); g3: INV PORT MAP (X(2), A2B); g4: NAND3 PORT MAP (X(2), A1B, A0B, Z1); g5: NAND3 PORT MAP (X(0), A1B, A2B, Z2); g6: NAND3 PORT MAP (X(0), X(1), X(2), Z3); g7: NAND3 PORT MAP (X(1), A2B, A0B, Z4); g8: NAND4 PORT MAP (Z1, Z2, Z3, Z4, Z); end Structural;

15 © Dr. Alaaeldin Amin 15 C0 Odd-Parity (OPAR3) g8 architecture Structural of OPAR3 is Component INV PORT( Ipt: in BIT; Opt: out BIT); end Component ; Component NAND3 PORT( I1, I2, I3: in BIT; O: out BIT); end Component ; Component NAND4 PORT( I1, I2, I3, I4: in BIT; O: out BIT); end Component ; -- SIGNAL A1B, A2B, A0B, Z1, Z2, Z3, Z4: BIT; begin g1: INV PORT MAP (X(0), A0B); g2: INV PORT MAP (X(1), A1B); g3: INV PORT MAP (X(2), A2B); g4: NAND3 PORT MAP (X(2), A1B, A0B, Z1); g5: NAND3 PORT MAP (X(0), A1B, A2B, Z2); g6: NAND3 PORT MAP (X(0), X(1), X(2), Z3); g7: NAND3 PORT MAP (X(1), A2B, A0B, Z4); g8: NAND4 PORT MAP (Z1, Z2, Z3, Z4, Z); end Structural;

16 © Dr. Alaaeldin Amin 16 Top Structural level of ones_cnt architecture Structural of ONES_CNT is COMPONENT MAJ3 PORT( X: in BIT_Vector(0 to 2); Z: out BIT); END COMPONENT; COMPONENT OPAR3 PORT( X: in BIT_Vector(0 to 2); Z: out BIT); END COMPONENT; -- begin -- Instantiate Components -- c1: MAJ3 PORT MAP (A, C(1)); c2: OPAR3 PORT MAP (A, C(0)); end Structural;

17 © Dr. Alaaeldin Amin 17 Behavioral definition of lower level components entity INV is PORT( Ipt: in BIT; Opt: out BIT); end INV; -- architecture behavior of INV is begin Opt <= not Ipt; end behavior; entity NAND2 is PORT( I1, I2: in BIT; O: out BIT); end NAND2; -- architecture behavior of NAND2 is begin O <= not (I1 and I2); end behavior; Similarly Other Lower Level Gates Are Defined

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