1. EE898.02 Architecture of Digital Systems Lecture 3 Cache Memory
Oct. 8, 2004
Prof. Seok-Bum Ko
Electrical Engineering
University of Saskatchewan

2. Question: Who Cares About the Memory Hierarchy?
CPU-DRAM Gap
1980: no cache in µproc; level cache on chip (1989 first Intel µproc with a cache on chip)
µProc
60%/yr.
DRAM
7%/yr. 1 10
100
1000
1980
1981
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
CPU
1982
Processor-Memory
Performance Gap: (grows 50% / year)
Performance
“Moore’s Law”
“Less’ Law?”
Y-axis is performance
X-axis is time
Latency
Cliché:
Not e that x86 didn’t have cache on chip until 1989

3. What is a cache?
Small, fast storage used to improve average access time to slow memory.
Exploits spatial and temporal locality
In computer architecture, almost everything is a cache!
Registers a cache on variables
First-level cache a cache on second-level cache
Second-level cache a cache on memory
Memory a cache on disk (virtual memory)
TLB a cache on page table
Branch-prediction a cache on prediction information?
Proc/Regs
L1-Cache
Bigger
Faster
L2-Cache
Memory
Disk, Tape, etc.

4. Levels of the Memory Hierarchy
Upper Level
Capacity
Access Time
Cost
Staging
Xfer Unit
faster
CPU Registers
100s Bytes
<1s ns
Registers
Instr. Operands
prog./compiler
1-8 bytes
Cache
10s-100s K Bytes
1-10 ns
$10/ MByte
Cache
cache cntl
8-128 bytes
Blocks
Main Memory
M Bytes
100ns- 300ns
$1/ MByte
Memory OS
512-4K bytes
Pages
Disk
10s G Bytes, 10 ms (10,000,000 ns)
$0.0031/ MByte
Disk
user/operator
Mbytes
Files
Larger
Tape
infinite
sec-min
$0.0014/ MByte
Tape
Lower Level

5. The Principle of Locality
Program access a relatively small portion of the address space at any instant of time.
Two Different Types of Locality:
Temporal Locality (Locality in Time): If an item is referenced, it will tend to be referenced again soon (e.g., loops, reuse)
Spatial Locality (Locality in Space): If an item is referenced, items whose addresses are close by tend to be referenced soon (e.g., straightline code, array access)
Last 15 years, HW (hardware) relied on locality for speed
The principle of locality states that programs access a relatively small portion of the address space at any instant of time.
This is kind of like in real life, we all have a lot of friends. But at any given time most of us can only keep in touch with a small group of them.
There are two different types of locality: Temporal and Spatial. Temporal locality is the locality in time which says if an item is referenced, it will tend to be referenced again soon.
This is like saying if you just talk to one of your friends, it is likely that you will talk to him or her again soon.
This makes sense. For example, if you just have lunch with a friend, you may say, let’s go to the ball game this Sunday. So you will talk to him again soon.
Spatial locality is the locality in space. It says if an item is referenced, items whose addresses are close by tend to be referenced soon.
Once again, using our analogy. We can usually divide our friends into groups. Like friends from high school, friends from work, friends from home.
Let’s say you just talk to one of your friends from high school and she may say something like: “So did you hear so and so just won the lottery.”
You probably will say NO, I better give him a call and find out more.
So this is an example of spatial locality. You just talked to a friend from your high school days. As a result, you end up talking to another high school friend. Or at least in this case, you hope he still remember you are his friend.
+3 = 10 min. (X:50)

6. Memory Hierarchy: Terminology
Hit: data appears in some block in the upper level (example: Block X)
Hit Rate: the fraction of memory access found in the upper level
Hit Time: Time to access the upper level which consists of
RAM access time + Time to determine hit/miss
Miss: data needs to be retrieved from a block in the lower level (Block Y)
Miss Rate = 1 - (Hit Rate)
Miss Penalty: Time to replace a block in the upper level +
Time to deliver the block the processor
Lower Level
Memory
Upper Level
To Processor
From Processor
Blk X
Blk Y
A HIT is when the data the processor wants to access is found in the upper level (Blk X).
The fraction of the memory access that are HIT is defined as HIT rate.
HIT Time is the time to access the Upper Level where the data is found (X). It consists of:
(a) Time to access this level.
(b) AND the time to determine if this is a Hit or Miss.
If the data the processor wants cannot be found in the Upper level. Then we have a miss and we need to retrieve the data (Blk Y) from the lower level.
By definition (definition of Hit: Fraction), the miss rate is just 1 minus the hit rate.
This miss penalty also consists of two parts:
(a) The time it takes to replace a block (Blk Y to BlkX) in the upper level.
(b) And then the time it takes to deliver this new block to the processor.
It is very important that your Hit Time to be much much smaller than your miss penalty. Otherwise, there will be no reason to build a memory hierarchy.
+2 = 14 min. (X:54)

7. Cache Measures Hit rate: fraction found in that level
So high that usually talk about Miss rate
Miss rate fallacy: as MIPS to CPU performance, miss rate to average memory access time in memory
Average memory-access time = Hit time + Miss rate x Miss penalty (ns or clocks)
Miss penalty: time to replace a block from lower level, including time to replace in CPU
access time: time to lower level
= f(latency to lower level)
transfer time: time to transfer block
= f(between upper & lower levels)

8. Simplest Cache: Direct Mapped
Memory Address
Memory
4 Byte Direct Mapped Cache 1
Cache Index 2 3 1 4 2 5 3 6
Location 0 can be occupied by data from:
Memory location 0, 4, 8, ... etc.
In general: any memory location whose 2 LSBs of the address are 0s
Address<1:0> => cache index
Which one should we place in the cache?
How can we tell which one is in the cache? 7 8 9 A
Let’s look at the simplest cache one can build. A direct mapped cache that only has 4 bytes.
In this direct mapped cache with only 4 bytes, location 0 of the cache can be occupied by data form memory location 0, 4, 8, C, ... and so on.
While location 1 of the cache can be occupied by data from memory location 1, 5, 9, ... etc.
So in general, the cache location where a memory location can map to is uniquely determined by the 2 least significant bits of the address (Cache Index).
For example here, any memory location whose two least significant bits of the address are 0s can go to cache location zero.
With so many memory locations to chose from, which one should we place in the cache?
Of course, the one we have read or write most recently because by the principle of temporal locality, the one we just touch is most likely to be the one we will need again soon.
Of all the possible memory locations that can be placed in cache Location 0, how can we tell which one is in the cache?
+2 = 22 min. (Y:02) B C D E F

9. 1 KB Direct Mapped Cache, 32B blocks
For a 2 ** N byte cache:
The uppermost (32 - N) bits are always the Cache Tag
The lowest M bits are the Byte Select (Block Size = 2 ** M) 31 9 4
Cache Tag
Example: 0x50
Cache Index
Byte Select
Ex: 0x01
Ex: 0x00
Stored as part
of the cache “state”
Valid Bit
Cache Tag
Cache Data :
Byte 31
Byte 1
Byte 0 :
Let’s use a specific example with realistic numbers: assume we have a 1 KB direct mapped cache with block size equals to 32 bytes.
In other words, each block associated with the cache tag will have 32 bytes in it (Row 1).
With Block Size equals to 32 bytes, the 5 least significant bits of the address will be used as byte select within the cache block.
Since the cache size is 1K byte, the upper 32 minus 10 bits, or 22 bits of the address will be stored as cache tag.
The rest of the address bits in the middle, that is bit 5 through 9, will be used as Cache Index to select the proper cache entry.
+2 = 30 min. (Y:10)
0x50
Byte 63
Byte 33
Byte 32 1 2 3 : : : :
Byte 1023
Byte 992 31

10. Two-way Set Associative Cache
N-way set associative: N entries for each Cache Index
N direct mapped caches operates in parallel (N typically 2 to 4)
Example: Two-way set associative cache
Cache Index selects a “set” from the cache
The two tags in the set are compared in parallel
Data is selected based on the tag result
Cache Index
Valid
Cache Tag
Cache Data
Cache Data
Cache Block 0
Cache Tag
Valid :
Cache Block 0 : : :
This is called a 2-way set associative cache because there are two cache entries for each cache index. Essentially, you have two direct mapped cache works in parallel.
This is how it works: the cache index selects a set from the cache. The two tags in the set are compared in parallel with the upper bits of the memory address.
If neither tag matches the incoming address tag, we have a cache miss.
Otherwise, we have a cache hit and we will select the data on the side where the tag matches occur.
This is simple enough. What is its disadvantages?
+1 = 36 min. (Y:16)
Compare
Adr Tag
Compare 1
Sel1
Mux
Sel0 OR
Cache Block
Hit

11. Disadvantage of Set Associative Cache
N-way Set Associative Cache v. Direct Mapped Cache:
N comparators vs. 1
Extra MUX delay for the data
Data comes AFTER Hit/Miss
In a direct mapped cache, Cache Block is available BEFORE Hit/Miss:
Possible to assume a hit and continue. Recover later if miss.
Cache Data
Cache Block 0
Cache Tag
Valid :
Cache Index
Mux 1
Sel1
Sel0
Cache Block
Compare
Adr Tag OR
Hit
First of all, a N-way set associative cache will need N comparators instead of just one comparator (use the right side of the diagram for direct mapped cache).
A N-way set associative cache will also be slower than a direct mapped cache because of this extra multiplexer delay.
Finally, for a N-way set associative cache, the data will be available AFTER the hit/miss signal becomes valid because the hit/mis is needed to control the data MUX.
For a direct mapped cache, that is everything before the MUX on the right or left side, the cache block will be available BEFORE the hit/miss signal (AND gate output) because the data does not have to go through the comparator.
This can be an important consideration because the processor can now go ahead and use the data without knowing if it is a Hit or Miss. Just assume it is a hit.
Since cache hit rate is in the upper 90% range, you will be ahead of the game 90% of the time and for those 10% of the time that you are wrong, just make sure you can recover.
You cannot play this speculation game with a N-way set-associatvie cache because as I said earlier, the data will not be available to you until the hit/miss signal is valid.
+2 = 38 min. (Y:18)

12. 4 Questions for Memory Hierarchy
Q1: Where can a block be placed in the upper level? (Block placement)
Q2: How is a block found if it is in the upper level? (Block identification)
Q3: Which block should be replaced on a miss? (Block replacement)
Q4: What happens on a write? (Write strategy)

13. Q1: Where can a block be placed in the upper level?
Block 12 placed in 8 block cache:
Fully associative, direct mapped, 2-way set associative
S.A. Mapping = Block Number Modulo Number Sets
Direct Mapped
(12 mod 8) = 4
2-Way Assoc
(12 mod 4) = 0
Full Mapped
Cache
Memory

14. Q2: How is a block found if it is in the upper level?
Tag on each block
No need to check index or block offset
Increasing associativity shrinks index, expands tag
Block
Offset
Block Address
Index
Tag

15. Q3: Which block should be replaced on a miss?
Easy for Direct Mapped
Set Associative or Fully Associative:
Random
LRU (Least Recently Used)
FIFO (First In First Out)
Ref. fig. 5.6, p. 401 (3rd edition)

16. Q4: What happens on a write?
Write through—The information is written to both the block in the cache and to the block in the lower-level memory.
Write back—The information is written only to the block in the cache. The modified cache block is written to main memory only when it is replaced.
is block clean or dirty?
Pros and Cons of each?
WT: read misses cannot result in writes
WB: no repeated writes to the same location
WT always combined with write buffers so that don’t wait for lower level memory

17. A Modern Memory Hierarchy
By taking advantage of the principle of locality:
Present the user with as much memory as is available in the cheapest technology.
Provide access at the speed offered by the fastest technology.
Control
Datapath
Secondary
Storage
(Disk)
Processor
Registers
Main
Memory
(DRAM)
Second
Level
Cache
(SRAM)
On-Chip 1s
10,000,000s
(10s ms)
Speed (ns):
10s
100s Gs
Size (bytes): Ks Ms
Tertiary
(Disk/Tape)
10,000,000,000s
(10s sec) Ts
The design goal is to present the user with as much memory as is available in the cheapest technology (points to the disk).
While by taking advantage of the principle of locality, we like to provide the user an average access speed that is very close to the speed that is offered by the fastest technology.
(We will go over this slide in details in the next lecture on caches).
+1 = 16 min. (X:56)

18. Example: Harvard Architecture
Unified vs. Separate I&D (Harvard)
Table on page 384 (2nd edition):
16KB I&D: Inst miss rate=0.64%, Data miss rate=6.47%
32KB unified: Aggregate miss rate=1.99%
Which is better (ignore L2 cache)?
Assume 33% data ops  75% accesses from instructions (1.0/1.33)
hit time=1, miss time=50
Note that data hit has 1 stall for unified cache (only one port)
AMATHarvard=75%x(1+0.64%x50)+25%x(1+6.47%x50) = 2.05
AMATUnified=75%x(1+1.99%x50)+25%x( %x50)= 2.24
Proc
I-Cache-1
Unified
Cache-1
Cache-2
D-Cache-1

19. Improving Cache Performance
1. Reduce the miss rate,
2. Reduce the miss penalty, or
3. Reduce the time to hit in the cache.

20. Reducing Misses Classifying Misses: 3 Cs
Compulsory—The first access to a block is not in the cache, so the block must be brought into the cache. Also called cold start misses or first reference misses. (Misses in even an Infinite Cache)
Capacity—If the cache cannot contain all the blocks needed during execution of a program, capacity misses will occur due to blocks being discarded and later retrieved. (Misses in Fully Associative Size X Cache)
Conflict—If block-placement strategy is set associative or direct mapped, conflict misses (in addition to compulsory & capacity misses) will occur because a block can be discarded and later retrieved if too many blocks map to its set. Also called collision misses or interference misses. (Misses in N-way Associative, Size X Cache)
More recent, 4th “C”:
Coherence - Misses caused by cache coherence.
Intuitive Model by Mark Hill

21. 1. Reduce Misses via Larger Block Size

22. 2. Reduce Misses via Higher Associativity
2:1 Cache Rule:
Miss Rate DM cache size N ­ Miss Rate 2-way cache size N/2

23. 3. Reducing Misses via a “Victim Cache”
How to combine fast hit time of direct mapped yet still avoid conflict misses?
Add buffer to place data discarded from cache
Jouppi [1990]: 4-entry victim cache removed 20% to 95% of conflicts for a 4 KB direct mapped data cache
Used in Alpha, HP machines
TAGS
DATA
Tag and Comparator
One Cache line of Data
Tag and Comparator
One Cache line of Data
Tag and Comparator
One Cache line of Data
Tag and Comparator
One Cache line of Data
To Next Lower Level In
Hierarchy

24. 4. Reducing Misses via “Pseudo-Associativity”
How to combine fast hit time of Direct Mapped and have the lower conflict misses of 2-way SA cache?
Divide cache: on a miss, check other half of cache to see if there, if so have a pseudo-hit (slow hit)
Drawback: CPU pipeline is hard if hit takes 1 or 2 cycles
Better for caches not tied directly to processor (L2)
Used in MIPS R1000 L2 cache, similar in UltraSPARC
Hit Time
Pseudo Hit Time
Miss Penalty
Time

25. 5. Reducing Misses by Hardware Prefetching of Instructions & Data
E.g., Instruction Prefetching
Alpha fetches 2 blocks on a miss
Extra block placed in “stream buffer”
On miss check stream buffer
Works with data blocks too:
Jouppi [1990] 1 data stream buffer got 25% misses from 4KB cache; 4 streams got 43%
Palacharla & Kessler [1994] for scientific programs for 8 streams got 50% to 70% of misses from 2 64KB, 4-way set associative caches
Prefetching relies on having extra memory bandwidth that can be used without penalty

26. 6. Reducing Misses by Software Prefetching Data
Data Prefetch
Load data into register (HP PA-RISC loads)
Cache Prefetch: load into cache (MIPS IV, PowerPC, SPARC v. 9)
Special prefetching instructions cannot cause faults; a form of speculative execution
Prefetching comes in two flavors:
Binding prefetch: Requests load directly into register.
Must be correct address and register!
Non-Binding prefetch: Load into cache.
Can be incorrect. Frees HW/SW to guess!
Issuing Prefetch Instructions takes time
Is cost of prefetch issues < savings in reduced misses?
Higher superscalar reduces difficulty of issue bandwidth

27. 7. Reducing Misses by Compiler Optimizations
McFarling [1989] reduced caches misses by 75% on 8KB direct mapped cache, 4 byte blocks in software
Instructions
Reorder procedures in memory so as to reduce conflict misses
Profiling to look at conflicts(using tools they developed)
Data
Merging Arrays: improve spatial locality by single array of compound elements vs. 2 arrays
Loop Interchange: change nesting of loops to access data in order stored in memory
Loop Fusion: Combine 2 independent loops that have same looping and some variables overlap
Blocking: Improve temporal locality by accessing “blocks” of data repeatedly vs. going down whole columns or rows

28. Merging Arrays Example
/* Before: 2 sequential arrays */
int val[SIZE];
int key[SIZE];
/* After: 1 array of structures */
struct merge {
int val;
int key; };
struct merge merged_array[SIZE];
Reducing conflicts between val & key; improve spatial locality

29. Loop Interchange Example
/* Before */
for (k = 0; k < 100; k = k+1)
for (j = 0; j < 100; j = j+1)
for (i = 0; i < 5000; i = i+1)
x[i][j] = 2 * x[i][j];
/* After */
Sequential accesses instead of striding through memory every 100 words; improved spatial locality

30. Loop Fusion Example
/* Before */
for (i = 0; i < N; i = i+1)
for (j = 0; j < N; j = j+1)
a[i][j] = 1/b[i][j] * c[i][j];
d[i][j] = a[i][j] + c[i][j];
/* After */
{ a[i][j] = 1/b[i][j] * c[i][j];
d[i][j] = a[i][j] + c[i][j];}
2 misses per access to a & c vs. one miss per access; improve temporal locality

31. Blocking Example Two Inner Loops:
/* Before */
for (i = 0; i < N; i = i+1)
for (j = 0; j < N; j = j+1)
{r = 0;
for (k = 0; k < N; k = k+1){
r = r + y[i][k]*z[k][j];};
x[i][j] = r; };
Two Inner Loops:
Read all NxN elements of z[]
Read N elements of 1 row of y[] repeatedly
Write N elements of 1 row of x[]
Capacity Misses a function of N & Cache Size:
2N3 + N2 => (assuming no conflict; otherwise …)
Idea: compute on BxB submatrix that fits

32. Blocking Example B called Blocking Factor
/* After */
for (jj = 0; jj < N; jj = jj+B)
for (kk = 0; kk < N; kk = kk+B)
for (i = 0; i < N; i = i+1)
for (j = jj; j < min(jj+B-1,N); j = j+1)
{r = 0;
for (k = kk; k < min(kk+B-1,N); k = k+1) {
r = r + y[i][k]*z[k][j];};
x[i][j] = x[i][j] + r; };
B called Blocking Factor
Capacity Misses from 2N3 + N2 to N3/B+2N2
Conflict Misses Too?
Improve temporal locality by accessing “blocks” of data repeatedly vs. going down whole columns or rows

33. Summary: Miss Rate Reduction
3 Cs: Compulsory, Capacity, Conflict
1. Reduce Misses via Larger Block Size
2. Reduce Misses via Higher Associativity
3. Reducing Misses via Victim Cache
4. Reducing Misses via Pseudo-Associativity
5. Reducing Misses by HW Prefetching Instr, Data
6. Reducing Misses by SW Prefetching Data
7. Reducing Misses by Compiler Optimizations
Prefetching comes in two flavors:
Binding prefetch: Requests load directly into register.
Must be correct address and register!
Non-Binding prefetch: Load into cache.
Can be incorrect. Frees HW/SW to guess!

34. Improving Cache Performance
1. Reduce the miss rate,
2. Reduce the miss penalty, or
3. Reduce the time to hit in the cache.

35. Write Policy: Write-Through vs Write-Back
Write-through: all writes update cache and underlying memory/cache
Can always discard cached data - most up-to-date data is in memory
Cache control bit: only a valid bit
Write-back: all writes simply update cache
Can’t just discard cached data - may have to write it back to memory
Cache control bits: both valid and dirty bits
Other Advantages:
Write-through:
memory (or other processors) always have latest data
Simpler management of cache
Write-back:
much lower bandwidth, since data often overwritten multiple times
Better tolerance to long-latency memory?

36. Write Policy 2: Write Allocate vs Non-Allocate (What happens on write-miss)
Write allocate: allocate new cache line in cache
Usually means that you have to do a “read miss” to fill in rest of the cache-line!
Alternative: per/word valid bits
Write non-allocate (or “write-around”):
Simply send write data through to underlying memory/cache - don’t allocate new cache line!

37. 1. Reducing Miss Penalty: Read Priority over Write on Miss
buffer
CPU
in out
DRAM
(or lower mem)
Write Buffer

38. 1. Reducing Miss Penalty: Read Priority over Write on Miss
Write-through with write buffers offer RAW conflicts with main memory reads on cache misses
If simply wait for write buffer to empty, might increase read miss penalty (old MIPS 1000 by 50% )
Check write buffer contents before read; if no conflicts, let the memory access continue
Write-back also want buffer to hold misplaced blocks
Read miss replacing dirty block
Normal: Write dirty block to memory, and then do the read
Instead copy the dirty block to a write buffer, then do the read, and then do the write
CPU stall less since restarts as soon as do read

39. 2. Reducing Miss Penalty: Early Restart and Critical Word First
Don’t wait for full block to be loaded before restarting CPU
Early Restart—As soon as the requested word of the block arrives, send it to the CPU and let the CPU continue execution
Critical Word First—Request the missed word first from memory and send it to the CPU as soon as it arrives; let the CPU continue execution while filling the rest of the words in the block. Also called wrapped fetch and requested word first
Generally useful only in large blocks,
Spatial locality a problem; tend to want next sequential word, so not clear if benefit by early restart
block

40. 3. Reducing Miss Penalty: Non-blocking Caches to reduce stalls on misses
Non-blocking cache or lockup-free cache allow data cache to continue to supply cache hits during a miss
requires F/E bits on registers or out-of-order execution
requires multi-bank memories
“hit under miss” reduces the effective miss penalty by working during miss vs. ignoring CPU requests
“hit under multiple miss” or “miss under miss” may further lower the effective miss penalty by overlapping multiple misses
Significantly increases the complexity of the cache controller as there can be multiple outstanding memory accesses
Requires multiple memory banks (otherwise cannot support)
Pentium Pro allows 4 outstanding memory misses

41. 4. Add a second-level cache
L2 Equations
AMAT = Hit TimeL1 + Miss RateL1 x Miss PenaltyL1
Miss PenaltyL1 = Hit TimeL2 + Miss RateL2 x Miss PenaltyL2
AMAT = Hit TimeL1 +
Miss RateL1 x (Hit TimeL2 + Miss RateL2 + Miss PenaltyL2)
Definitions:
Local miss rate— misses in this cache divided by the total number of memory accesses to this cache (Miss rateL2)
Global miss rate—misses in this cache divided by the total number of memory accesses generated by the CPU (Miss RateL1 x Miss RateL2)
Global Miss Rate is what matters

42. Comparing Local and Global Miss Rates
32 KByte 1st level cache; Increasing 2nd level cache
Global miss rate close to single level cache rate provided L2 >> L1
Don’t use local miss rate
L2 not tied to CPU clock cycle!
Cost & A.M.A.T.
Generally Fast Hit Times and fewer misses
Since hits are few, target miss reduction
Linear
Cache Size
Log
Cache Size

43. Reducing Miss Penalty Summary
Four techniques
Read priority over write on miss
Early Restart and Critical Word First on miss
Non-blocking Caches (Hit under Miss, Miss under Miss)
Second Level Cache
Can be applied recursively to Multilevel Caches
Danger is that time to DRAM will grow with multiple levels in between
First attempts at L2 caches can make things worse, since increased worst case is worse

44. Improving Cache Performance
1. Reduce the miss rate,
2. Reduce the miss penalty, or
3. Reduce the time to hit in the cache.

45. 1. Fast Hit times via Small and Simple Caches
Why Alpha has 8KB Instruction and 8KB data cache + 96KB second level cache?
Small data cache and clock rate
Direct Mapped, on chip

46. 2. Fast hits by Avoiding Address Translation
CPU
CPU
CPU VA VA VA VA
Tags TB $ PA
Tags $ TB PA VA PA
L2 $ $ TB
MEM PA PA
MEM
MEM
Overlap $ access
with VA translation:
requires $ index to
remain invariant
across translation
Conventional
Organization
Virtually Addressed Cache
Translate only on miss
Synonym Problem

47. 2. Fast hits by Avoiding Address Translation
Send virtual address to cache? Called Virtually Addressed Cache or just Virtual Cache vs. Physical Cache
Every time process is switched logically must flush the cache; otherwise get false hits
Cost is time to flush + “compulsory” misses from empty cache
Dealing with aliases (sometimes called synonyms); Two different virtual addresses map to same physical address
I/O must interact with cache, so need virtual address
Solution to aliases
HW guarantees covers index field & direct mapped, they must be unique; called page coloring
Solution to cache flush
Add process identifier tag that identifies process as well as address within process: can’t get a hit if wrong process

48. 2. Fast Cache Hits by Avoiding Translation: Index with Physical Portion of Address
If index is physical part of address, can start tag access in parallel with translation so that can compare to physical tag
Limits cache to page size: what if want bigger caches and uses same trick?
Higher associativity moves barrier to right
Page coloring
Page Address
Page Offset
Address Tag
Index
Block Offset

49. What is the Impact of What You’ve Learned About Caches?
: Speed = ƒ(no. operations)
1990
Pipelined Execution & Fast Clock Rate
Out-of-Order execution
Superscalar Instruction Issue
1998: Speed = ƒ(non-cached memory accesses)
What does this mean for
Compilers?,Operating Systems?, Algorithms? Data Structures?