1. Noise Canceling in 1-D Data: Presentation #12 Seri Rahayu Abd Rauf Fatima Boujarwah Juan Chen Liyana Mohd Sharipp Arti Thumar M2 April 11 th, 2005 Final LVS and Simulation Overall Project Objective: Implementing Noise Cancellation Algorithm in Hardware Project Manager: Bobby Colyer

2. Status Design proposal (Done) Architecture proposal (Done) Size Estimates and Floorplan (Done) Gate Level Design - Schematics (Done) –Layout (Done) To be done: –Spice simulation (97%)

3. Last week’s Floorplan

4. LVSed Full-Chip Layout

5. LVS Output File Net-lists match

6. Final Poly Mask

7. Final Metal 1 Mask

8. Final Metal 2 Mask

9. Final Metal 3 Mask

10. Final Metal 4 Mask

11. The Chip Dimensions –Width = 373.0950µ –Height = 298.00µ Area = 111182.31 µ² Transistor count = 25153 –NMOS: 13407 –PMOS: 11746 Density = 0.23 trans/µ² Aspect ratio = 1: 1.25

12. Floating Point Adder 1

13. Floating Point Adder 2

14. Floating Point Adder 3

15. Multiplier 1 Final Simulations Results

16. Multiplier 1: Rise Time Rise Time: 48.3823 ps

17. Multiplier 2 Final Simulation Results

18. Multiplier 2: Rise Time Rise Time: 48.729 ps

19. Adder 3 Final Simulation Results

20. Adder 3: Rise Time Rise Time: 39.4352 ps

21. Full-Chip Critical Path Estimation

22. Challenges Adder 1&2 simulations Obtaining accurate full- chip simulation results

23. Questions?