1. Scalable Processor Architecture (SPARC) Jeff Miles Joel Foster Dhruv Vyas

2. Overview Designed to optimize compilers and pipelined hardware implementations Offers fast execution rates Engineered at Sun Microsystems in 1985 –Based on RISC I & II which were developed at Univ of Cal at Berkeley SPARC “register window” architecture

3. Features Performance and Economy –Simplified instruction set –Higher number of instructions with fewer transistors Scalability –Flexible integration of cache, memory and FPUs Open Architecture –Compatible technology to multiple vendors –Now allow access to CPU component techniques –Complete set of development tool available for h/w & s/w

4. Architecture RISC machine 64-bit addressing and 64-bit data Increased bandwidth Fault tolerance Nine stage pipeline; can do up to 4 instructions per cycle On-chip 16Kb data and instruct. Caches –With 2Mb external cache

7. Registers General purpose/ working data registers –IU’s ‘r’ registers –FPU’s ‘f’ registers Control status registers –IU control/status registers –FPU control/status registers –Coprocessor (CP) control/status registers

8. Registers Window Overlapping Each window shares its ins and outs with two adjacent windows –Incremented by a RESTORE instruction decremented by a SAVE instruction –Due to windowing the number available to software is 1 less than number implemented –When a register is full the outs of the newest window are the ins of the oldest, which still contain valid program data

10. IU Control/Status Registers Processor State Register (PSR) Window Invalid Mask (WIM) Multiply/Divide (Y) Program Counters (PC, nPC) Ancillary State Registers (ASR) Deferred-Trap Queue Trap Base Register (TBR)

11. IU Control/Status Registers Processor State Register (PSR) –Contains various fields that control and hold status information Window Invalid Mask (WIM) –To determine a window overflow or underflow ImplVerIccReservedECEFPILSPSETCWP W31W30W29-----------------------W1W0 31:2827:24 23:20 19:1413 12 11:8 7 6 5 4:0

12. Memory Each location identified by –Address Space Identifier (ASI) –64-bit address Real memory –No side effects I/O locations –Side effects

13. Snoop

14. Pipelining

15. Instruction Formats VIS – Visual Instruction Set –Visualization built into chip Examples of formats

20. What makes the CISC lock-up? Elegant forward looking branch instruction set –Compiler can go to different branches More complete testing of SPARC Simpler compiler design Better integration of OS interrupts to H/W interrupts Solaris has a tighter source code –Less devices to support

21. References Weaver, David/Tom Germond. SPARC Architecture Manual: Version 9, Prentice Hall.  1994. Stallings, William. Computer Organization and Architecture: 5 th Edition, Prentice Hall.  2000. Bresani, Fred. Systems Engineer, Sun Microsystems. http://www.sun.com http://www.sparc.com http://www.fujitsu.com