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CS294-6 Reconfigurable Computing Day4 September 3, 1998 VLSI Scaling
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Why Care? In this game, we must be able to predict the future Rapid technology advance Reason about changes and trends re-evaluate prior solutions given technology at time X.
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Scaling Premise: features scale “uniformly” –everything gets better in a predictable manner Parameters: – (lambda) -- Mead and Conway (class) –S -- Bohr –1/ -- Dennard
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Feature Size
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Scaling Channel Length (L) Channel Width (W) Oxide Thickness (T ox ) Doping (N a ) Voltage (V)
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Scaling Channel Length (L) Channel Width (W) Oxide Thickness (T ox ) Doping (N a ) 1/ Voltage (V)
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Effects? Area Capacitance Resistance Threshold (V th ) Current (I d ) Gate Delay ( gd ) Wire Delay ( wire ) Power
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Area L * W m m 50% area 2x capacity same area
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Area Perspective
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Capacitance Capacitance per unit area –C ox = SiO 2 /T ox –T ox T ox / –C ox C ox
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Capacitance Gate Capacitance –C gate = A*C ox – –C ox C ox –C gate C gate /
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Threshold Voltage
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V TH V TH
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Current Saturation Current –I d =( C OX /2)(W/L)(V gs -V TH ) 2 –V gs= V V –V TH V TH –W W –C ox C ox –I d I d
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Gate Delay gd =Q/I=(CV)/I V V I d I d C C / gd gd /
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Resistance R= L/(W*t) W W R R
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Wire Delay wire =R L C R R C C / wire wire …assuming (logical) wire lengths remain constant...
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Power Dissipation (Static) Resistive Power –P=V*I –V V –I d I d –P P
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Power Dissipation (Dynamic) Capacitive (Dis)charging –P=(1/2)CV 2 f –V V –C C / –P P Increase Frequency? –f f ? –P P
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Effects? Area 1/ Capacitance 1/ Resistance Threshold (V th ) 1/ Current (I d ) 1/ Gate Delay ( gd ) 1/ Wire Delay ( wire ) 1 Power 1/ 1/
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Delays? If delays in gates/switching? If delays in interconnect? Logical interconnect lengths?
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Delays? If delays in gates/switching? –Delay reduce with 1/
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Delays Logical capacities growing Wirelengths? –No locallity –Rent’s Rule L n (p-0.5) [p>0.5]
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Capacity Rent: IO=C*N p p>0.5 A C*N 2p Logical Area A C*N 2 2p N 2p N 2 2p N 2 p) N Sanity Check –p=1 –N 2 N –p~0.5 –N 2 N
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Compute Density >compute density scaling> gates dominate, p<0.5 moderate p, good fraction of gate delay large p (wires dominate area and delay)
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Power Density P P (static, or increase frequency) P P (dynamic, same freq.) P/A P/A … or … P/ A
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Scaling Summary Uniform scaling reasonably accurate for past couple of decades Area increase –Real capacity maybe a little less? Gate delay decreases (1/ ) Wire delay not decrease, maybe increase Overall delay decrease less than (1/ )
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