1. MINER A NuMI MINER A Director’s Review 10 January 2005 D. Casper UC Irvine Electronics and Data Acquisition D. Casper (Irvine) with P. Rubinov (Fermilab) D. Naples and V. Paolone (Pittsburgh)

2. MINER A NuMI MINER A Director’s Review 10 January 2005 D. Casper UC Irvine January 10, 2005Electronics and DAQ2 Outline  Overview  Responsibilities  Physics Requirements  Technical Review  Safety Issues  Costs  R&D Status and Plans

3. MINER A NuMI MINER A Director’s Review 10 January 2005 D. Casper UC Irvine January 10, 2005Electronics and DAQ3 Electronics in MINER A  Front-end Electronics t High-voltage for MAPMTs t Digitization t One board on each PMT box  DAQ and Slow Control t Front-end/computer interface t Distribute trigger and synchronization t Three VME crates + server  Power and Rack Protection t 7 kW required (includes MAPMTs) t 48 V supplies, fanouts and interlock provided by Fermilab t See D. Harris talk

4. MINER A NuMI MINER A Director’s Review 10 January 2005 D. Casper UC Irvine January 10, 2005Electronics and DAQ4 Front-End Responsibilities  Front-end Digitizer Boards t One board per MAPMT (64 channels), mounted outside PMT box t Programmable Cockroft/Walton HV supply, on removable daughter card t Discriminators t Analog pipeline t High- and low-gain QDC’s t TDC logic t LVDS interface to DAQ system  Design, Prototyping and Firmware t Fermilab (Rubinov) and Pittsburgh (Naples, Paolone)  Production, Testing and Installation t Pittsburgh Simplified schematic of front-end board

5. MINER A NuMI MINER A Director’s Review 10 January 2005 D. Casper UC Irvine January 10, 2005Electronics and DAQ5 DAQ Responsibilities  Key Component: Chain Read-Out Controller (CROC) t Each serves 4 chains of 12 front-end boards (48 × 64 = 3072 channels/ board) t Distribute synchronization signals from NuMI/MINOS t Pull data from front-end after spill t Pass configuration, HV control messages between DAQ computer and front-end  LVDS Chains t Support token-ring communication between CROC’s and front-end  VME Interface and Electronics t Two crates for CROCs, one for miscellaneous logic and monitoring t PCI/VME bridge  DAQ Computer  Design, Prototyping and Firmware t Fermilab (Rubinov) and Irvine (Casper)  Production, Testing and Software t Irvine

6. MINER A NuMI MINER A Director’s Review 10 January 2005 D. Casper UC Irvine January 10, 2005Electronics and DAQ6 Front-end Physics Requirements  Precision Coordinate Resolution and Tracking t Relies on charge-sharing between neighboring strips t Requires low-noise, single-PE sensitivity  Calorimetry, dE/dx and Particle Identification t Relies on specific ionization measurement t Requires large dynamic range (50  minimum ionizing) »High- and low-gain ADC channels for each pixel  Strange Particle, Muon Decay ID t Relies on timing t Requires few-ns time resolution on front-end, global synchronization »TDC functionality implemented in firmware  Pattern Recognition for Exclusive Reconstruction of Complex Topologies t Timing and 4-hit buffers/channel allow separation of multiple interactions in spill t Not multiplexed

7. MINER A NuMI MINER A Director’s Review 10 January 2005 D. Casper UC Irvine January 10, 2005Electronics and DAQ7 DAQ Physics Requirements  Modest Data Rate t Expect about 1 event per spill t Low occupancy per event t Two-second window to read digitizers before next spill arrives  Unbiased Trigger t Gate can be opened in advance of beam arrival (unbiased trigger) »No need for complicated trigger logic based on PMT signals t Collect cosmic rays with random gates (or something more sophisticated)  Global Synchronization t Requires high-bandwidth connection to front-end boards t LVDS chain

8. MINER A NuMI MINER A Director’s Review 10 January 2005 D. Casper UC Irvine January 10, 2005Electronics and DAQ8 High-Voltage  Cockroft-Walton power supply for MAPMT on daughter-card outside the PMT boxes t Allows easy maintenance and replacement without breaking light seal  Expected HV range: 700 – 800 V  Voltage under computer control and monitoring over LVDS chain  Controller based on Fermilab RMCC chip being developed for BTeV

9. MINER A NuMI MINER A Director’s Review 10 January 2005 D. Casper UC Irvine January 10, 2005Electronics and DAQ9 Charge Discrimination and Digitization  Charge digitization scheme is based on the TRiP chip developed by DØ t 16 discriminator channels/chip t 32 analog pipeline channels/chip »Up to four hits/channel/spill t Four chips per front-end board  Input signal for each pixel is passively divided into high- and low-gain ADC channels t Maintain single PE performance for charge-sharing t Increase dynamic range by ten for dE/dx measurement t 12-bit digitization

10. MINER A NuMI MINER A Director’s Review 10 January 2005 D. Casper UC Irvine January 10, 2005Electronics and DAQ10 Timing and Firmware  Each pixel’s discriminator latch is used to measure the time of the pulse t Important to separate multiple interaction in spill, identify delayed coincidence from strange particles  25 MHz Tevatron reference clock is multiplied by 4 in a Phase-Locked Loop, then phase-shifted by 90 degrees to give a “quadrature” clock with 2.5 ns resolution least-count.  A reprogrammable logic array controls the sequencing of timing and charge read-out, driven by a local oscillator  Digitized times and charges stored in onboard RAM for readout after spill

11. MINER A NuMI MINER A Director’s Review 10 January 2005 D. Casper UC Irvine January 10, 2005Electronics and DAQ11 LVDS Chains  All signals to and from front-end carried by LVDS rings t 12 front-end boards per chain t Transmit + Receive ports on each front-end board t Token ring protocol  Functionality t Read/write digital data in front-end memory t Open gate for spill in response to NuMI timing t Synchronization (1.5 – 2 ns jitter for 12-board ring) t Control and monitor HV t Reprogram FPGA firmware

12. MINER A NuMI MINER A Director’s Review 10 January 2005 D. Casper UC Irvine January 10, 2005Electronics and DAQ12 CROC Modules and VME  11 Chain Read-out Controllers, each controlling 4 LVDS rings t Two VME crates  Spill timing from NuMI using MINOS modules  Commercial VME hardware to measure spill timing, generate artificial triggers, etc. in third VME crate  Commercial PCI/VME interface to DAQ computer  Rack-mounted dual-CPU server for data acquisition and storage

13. MINER A NuMI MINER A Director’s Review 10 January 2005 D. Casper UC Irvine January 10, 2005Electronics and DAQ13 Safety Issues  Cables t LVDS cables will be halogen-free CAT-5e network cable t To be approved by Fermilab ES&H  Rack and electronics protection t Fuses on front-end board and power fanouts t A system to monitor hazards in the hall and automatically shut off power to the front-end electronics and DAQ (in the event of fire, flood, etc) will be provided by Fermilab  Cavern egress and installation t See installation talk by D. Harris

14. MINER A NuMI MINER A Director’s Review 10 January 2005 D. Casper UC Irvine January 10, 2005Electronics and DAQ14 Prototyping  16-channel front-end prototype successfully tested in Summer 2004 with invaluable Fermilab support t All charge and time digitization performance requirements satisfied or exceeded  LVDS interface and jitter tested with four front-end prototypes at FNAL, December 2004  Second-generation front-end board, with 64 channels and HV supply to be completed and tested by Q3 2005  CROC prototype to be completed and tested by Q4 2005

15. MINER A NuMI MINER A Director’s Review 10 January 2005 D. Casper UC Irvine January 10, 2005Electronics and DAQ15 Front-end Costs  Total Pittsburgh direct costs for front-end electronics: $453,293 t Fabricate 580 front-end boards (includes 15% spares): $351,480 ($606/board - $150 PC board, $336 components, $120 assembly) t Produce 2,500 TRiP chips: $70,000 t TRiP tester board: $15,000 t Front-end test set-up: $9,408 t Undergraduate labor: $7,405 t Total cost per detector channel: $14.62 t Includes 40-50% contingency  Fermilab contributions to front-end electronics: $202,500(+) t Design, Prototyping, Firmware (17.4 months Elec. Engineer): $195,000 t M&S for prototype: $7,500 t (+) 160 hours technician labor for prototype assembly

16. MINER A NuMI MINER A Director’s Review 10 January 2005 D. Casper UC Irvine January 10, 2005Electronics and DAQ16 DAQ Costs  Total Irvine direct costs for DAQ: $209,874 t VME crates and interface: $66,000 t Fabricate 16 CROC VME modules: $48,000 ($3,000 per board) t Commercial VME modules (TDC, pulser, etc): $20,000 t NuMI/MINOS timing modules: $18,000 t DAQ computer and software: $18,000 t LVDS cables: $15,750 t Prototyping and test hardware: $13,000 t Undergraduate labor: $11,124 t Total cost per detector channel: $6.78 t Includes 40% contingency on CROC, 20% on commercial items  Fermilab contributions: $133,500 t 1 year EE (design, prototyping and firmware): $130,000 t $3,500 M&S for prototype

17. MINER A NuMI MINER A Director’s Review 10 January 2005 D. Casper UC Irvine January 10, 2005Electronics and DAQ17 Schedule and Milestones End 2006 Electronics Complete

18. MINER A NuMI MINER A Director’s Review 10 January 2005 D. Casper UC Irvine January 10, 2005Electronics and DAQ18 Summary  Electronics/DAQ design already well-advanced t Overall cost: $21.40/channel, including EDIA, spares + contingency t Strongly leverages existing technology wherever possible  Most important technical risks already addressed t TRiP digitization/buffering scheme t Timing t LVDS interface  Plan for final design completed and tested in about 12 months  Production and check-out complete in about 24 months t Final boards to be used for PMT testing t About six months prior to detector installation