1. Core-based SoCs Testing Julien Pouget Embedded Systems Laboratory (ESLAB) Linköping University Julien Pouget Embedded Systems Laboratory (ESLAB) Linköping University

2. 2 Julien Pouget, IDA/SaS/ESLAB SoCs’ Testing Contents  Introduction  Introduction to SoCs’ testing  PhD work  On-going research and future work

3. 3 Julien Pouget, IDA/SaS/ESLAB SoCs’ Testing Introduction  B.Sc. Montpellier university, France 1998  Theoretical Physics & Electronics  M.Sc. LIRMM, Montpellier university, France 1999  Microelectronics  Ph.D LIRMM, Montpellier university, France 2002  SoCs’ testing: Test Scheduling and Architectural Solutions

4. 4 Julien Pouget, IDA/SaS/ESLAB SoCs’ Testing Contents  Introduction  Introduction to SoCs’ testing  PhD work  On-going research and future work

5. 5 Julien Pouget, IDA/SaS/ESLAB SoCs’ Testing Introduction to SoCs’ Testing PCBs SoCs All functions are implemented on the same die

6. 6 Julien Pouget, IDA/SaS/ESLAB SoCs’ Testing Introduction to SoCs’ Testing  New problems  Accessibility  Power (test …)  Number of test patterns  Test time  Circuit test techniques  External test Memory depth problems Pin number limited Reduced accessibility to system I/Os  BIST Improved accessibility Area overhead, DfT necessary Isolation IP: structure?  External-BIST Test Trade-off…

7. 7 Julien Pouget, IDA/SaS/ESLAB SoCs’ Testing Introduction to SoCs’ Testing  Core providers  System designer System designer issue: adapt test architectures for every core in the design flow of the system  Test architecture normalisation for SoCs -P1500 Standard-  Core access logic harmonisation  Interface system/cores (TAM) design by system designers

8. 8 Julien Pouget, IDA/SaS/ESLAB SoCs’ Testing Introduction to SoCs’ Testing – P1500  Core wrapper  Test Access Mechanism

9. 9 Julien Pouget, IDA/SaS/ESLAB SoCs’ Testing Contents  Introduction  Introduction to SoCs’ testing  PhD work  On-going research and future work

10. 10 Julien Pouget, IDA/SaS/ESLAB SoCs’ Testing PhD Research Work  3 steps  Research direction Test schemes comparison  Wrapper Design Heuristic Including P1500 mandatory modes Test time minimization Optimized connectivity  TAM Design Bus based approach Co optimization mapping/scheduling

11. 11 Julien Pouget, IDA/SaS/ESLAB SoCs’ Testing PhD Research Work  Test controllers implementation  Test schemes comparison  Test time  Area overhead  Bus width  Algorithmic complexity  ST 0,18µm implementation Solution 1      Test time Solution 2Solution 3 Solution 1 TAM – #E/S Controller Area (BIST) Solution 2Solution 3   Solution 1 Solution 2 Solution 3 Fixed Sessions Variable Sessions Without session

12. 12 Julien Pouget, IDA/SaS/ESLAB SoCs’ Testing PhD Research Work  Core Test Interface Design (Wrapper)  TAM width used/core  core test time, global TAM  Bandwidth limitation for test  P1500 mandatory modes consideration  Normal mode (functional mode)  Core Test  Interconnections test  Bypass Heuristic :  I: W limit, core structure  O: W needed, T min, wrapper structure

13. 13 Julien Pouget, IDA/SaS/ESLAB SoCs’ Testing PhD Research Work Pareto optimal points

14. 14 Julien Pouget, IDA/SaS/ESLAB SoCs’ Testing PhD Research Work  TAM Design  Wrapper built with the presented heuristic: W i and T i chosen by user for each core  Goal: Test Access Mechanism design Bus based solution Total test time minimisation W total minimisation

15. 15 Julien Pouget, IDA/SaS/ESLAB SoCs’ Testing PhD Research Work  TAM Design  Exact method to generate the whole possible solution space Mathematic modelisation: Hypergraphs representing all the incompatibility possibilities  Mapping: bus assignation Fast Heuristic  Scheduling Fast Heuristic Power constraints Incompatibilities Precedence constraints 4(11)

16. 16 Julien Pouget, IDA/SaS/ESLAB SoCs’ Testing Contents  Introduction  Introduction to SoCs’ testing  PhD work  On-going research and future work

17. 17 Julien Pouget, IDA/SaS/ESLAB SoCs’ Testing On-going Research and Future Work  Test Scheduling based on Defect Probability  SoC approach: Test process ended as soon as a defect is detected ”abort-on-fail”  Estimated Test Time determined by a probabilistic formula using several schemes: Sequential testing with fixed test times Sequential testing with flexible test times Concurrent testing with fixed test times Concurrent testing with flexible test times  Wrapper values pre-determined using the tools from PhD work 10 cores with 10 stages each means 10 10 configuration possibilities !!!

18. 18 Julien Pouget, IDA/SaS/ESLAB SoCs’ Testing On-going Research and Future Work  Solution: heuristic  Based on a ”schedule ASAP” concept maximizing the TAM use  Allows reduced computation time  Results close to optimal solutions (validated on small examples)  Next step - Close future  Heuristic implementation Allow exploiting all the results from the wrapper design Will be applied on ITC’02 new coded benchmarks  Other possible algorithms to implement For example maximising the intermediate test time

19. 19 Julien Pouget, IDA/SaS/ESLAB SoCs’ Testing On-going Research and Future Work  Low Heuristic complexity  Aim: fix the NP complete problem of bin-packing  Use of the defect probabilities to schedule the tests 2 0,7 10 20 2 500 0005 000 0007 500 000 3 0,85 W 1 0,9 4 0,85 t 2 0,7 10 20 2 500 0005 000 0007 500 000 3 0,85 W 1 0,9 4 0,85 t T=4 872 349 cycles T p =3 235 990 cycles  Time Tp weighted by pass probabilities  Maximisation of TAM width use choosing the adapted W i /t i

20. 20 Julien Pouget, IDA/SaS/ESLAB SoCs’ Testing On-going Research and Future Work  Networks-on-chip  Future: hundreds of elements on a chip: Bus based solutions  Network based communications  Hardware/Software components Software already tested Hardware tested in production: new issue  Power problems  Resource sharing problems  Timing problems  Future focus: test of network-on-chip architectures

21. Questions?