1. 4/27/2006 ELEC7250: White 1 ELEC7250 VLSI Testing: Final Project Andrew White

2. 4/27/2006 ELEC7250: White 2 Overview Problem Description PlanResultsDemonstration

3. 4/27/2006 ELEC7250: White 3 Plan Compiler –Hierarchical bench formats are flattened Logic Simulator –Used simulation table and test vectors –Two states (1,0)

4. 4/27/2006 ELEC7250: White 4 Plan Algorithm –Input vector is propogated through to the output –Traverse through the gates in levels

5. 4/27/2006 ELEC7250: White 5 Results

6. 4/27/2006 ELEC7250: White 6 Results

7. 4/27/2006 ELEC7250: White 7 Plan Due to long logic simulations –Parallelize the problem Parallel Approach –Same algorithm as the sequential approach –Main node broadcasts the simulation table to all other nodes –Main node reads in test vector file and evenly distributes vectors to all other nodes –Each node computes vector values and reports the results to the main node

8. 4/27/2006 ELEC7250: White 8 Results

9. 4/27/2006 ELEC7250: White 9 Fault Diagnosis Find faulty vector Find faulty outputs Algorithm complexity

10. 4/27/2006 ELEC7250: White 10 Demonstration C17 Circuit

11. 4/27/2006 ELEC7250: White 11 Conclusion Questions/Comments?