1. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Chapter 2 The Microprocessor and its Architecture Barry B. Brey bbrey@ee.net

2. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Programming Model

3. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e General-Purpose Registers Named storage locations inside the CPU, optimized for speed.

4. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Accessing Parts of Registers Use 8-bit name, 16-bit name, or 32-bit name Use 8-bit name, 16-bit name, or 32-bit name Applies to EAX, EBX, ECX, and EDX Applies to EAX, EBX, ECX, and EDX

5. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e General-Purpose Registers The top portion of the programming model contains the general purpose registers: EAX, EBX, ECX, EDX, EBP, ESI, and EDI. The top portion of the programming model contains the general purpose registers: EAX, EBX, ECX, EDX, EBP, ESI, and EDI. These registers, although general in nature, each have special purposes and names. These registers, although general in nature, each have special purposes and names. EAX – Accumulator (as general as they come) used also as AX, AH, and AL EAX – Accumulator (as general as they come) used also as AX, AH, and AL EBX – Base Index often used to address memory data (BX, BH, and BL) EBX – Base Index often used to address memory data (BX, BH, and BL)

6. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e General-Purpose Registers (continued) ECX – count used in shifts and loops (CX, CH, and CL) ECX – count used in shifts and loops (CX, CH, and CL) EDX – data used in multiply and divide (DX, DH, and DL) EDX – data used in multiply and divide (DX, DH, and DL) EBP – base point used to address stack data (BP) EBP – base point used to address stack data (BP) ESI – source index addresses memory data (SI) ESI – source index addresses memory data (SI) EDI – destination index addresses memory data (DI) EDI – destination index addresses memory data (DI)

7. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Special-Purpose Registers The special purpose register each have specific tasks and are ESP, EIP, and EFLAGS The special purpose register each have specific tasks and are ESP, EIP, and EFLAGS ESP – address stack data used in functions (procedures) and temporary storage (SP) ESP – address stack data used in functions (procedures) and temporary storage (SP) EIP – addresses the next instruction in a program (IP) EIP – addresses the next instruction in a program (IP) EFLAGS – indicates conditions of the microprocessor (FLAGS) EFLAGS – indicates conditions of the microprocessor (FLAGS)

8. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Index and Base Registers Some registers have only a 16-bit name for their lower half: Some registers have only a 16-bit name for their lower half:

9. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Some Specialized Register Uses General-Purpose General-Purpose EAX – accumulator EAX – accumulator ECX – loop counter ECX – loop counter ESP – stack pointer ESP – stack pointer ESI, EDI – index registers ESI, EDI – index registers EBP – extended frame pointer (stack) EBP – extended frame pointer (stack) Segment Segment CS – code segment CS – code segment DS – data segment DS – data segment SS – stack segment SS – stack segment ES, FS, GS - additional segments ES, FS, GS - additional segments

10. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Some Specialized Register Uses (2 of 2) EIP – instruction pointer EIP – instruction pointer EFLAGS EFLAGS status and control flags status and control flags each flag is a single binary bit each flag is a single binary bit

11. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Status Flags Carry Carry unsigned arithmetic out of range unsigned arithmetic out of range Overflow Overflow signed arithmetic out of range signed arithmetic out of range Sign Sign result is negative result is negative Zero Zero result is zero result is zero Auxiliary Carry Auxiliary Carry carry from bit 3 to bit 4 carry from bit 3 to bit 4 Parity Parity sum of 1 bits is an even number sum of 1 bits is an even number

12. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7eEFLAGS

13. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e The Flags C – holds a carry or a borrow C – holds a carry or a borrow P – the parity flag (little use today) P – the parity flag (little use today) A – auxiliary flag used with DAA and DAS A – auxiliary flag used with DAA and DAS Z – zero Z – zero S – sign S – sign O – Overflow O – Overflow D – direction (used with string instructions) D – direction (used with string instructions) I – interrupt (interrupt on/off) I – interrupt (interrupt on/off) T – trace flag (trace on/off) T – trace flag (trace on/off)

14. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Newer Flag Bits IOPL – I/O privilege level for Windows IOPL – I/O privilege level for Windows NT – nested task NT – nested task RF – resume flag RF – resume flag VM – virtual mode VM – virtual mode AC – alignment check AC – alignment check VIF – virtual interrupt VIF – virtual interrupt VIP – virtual interrupt pending VIP – virtual interrupt pending ID = CPUID instruction available ID = CPUID instruction available

15. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Real-Address mode 1 MB RAM maximum addressable 1 MB RAM maximum addressable Application programs can access any area of memory Application programs can access any area of memory Single tasking Single tasking Supported by MS-DOS operating system Supported by MS-DOS operating system

16. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Segmented Memory Segmented memory addressing: absolute (linear) address is a combination of a 16-bit segment value added to a 16-bit offset linear addresses one segment

17. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Calculating Linear Addresses Given a segment address, multiply it by 16 (add a hexadecimal zero), and add it to the offset Given a segment address, multiply it by 16 (add a hexadecimal zero), and add it to the offset Example: convert 08F1:0100 to a linear address Example: convert 08F1:0100 to a linear address Adjusted Segment value: 0 8 F 1 0 Add the offset: 0 1 0 0 Linear address: 0 9 0 1 0

18. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Your turn... What linear address corresponds to the segment/offset address 028F:0030? 028F0 + 0030 = 02920 Always use hexadecimal notation for addresses.

19. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Your turn... What segment addresses correspond to the linear address 28F30h? Many different segment-offset addresses can produce the linear address 28F30h. For example: 28F0:0030, 28F3:0000, 28B0:0430,...

20. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Segment Register The segment registers are: CS (code), DS (data), ES (extra), SS (stack), FS, and GS. The segment registers are: CS (code), DS (data), ES (extra), SS (stack), FS, and GS. Segment registers address a section of memory in a program. A segment is either 64K in length (real mode) or up to 4G in length (protected mode). Segment registers address a section of memory in a program. A segment is either 64K in length (real mode) or up to 4G in length (protected mode). All code (programs) reside in the code segment. All code (programs) reside in the code segment.

21. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Real Mode Memory Addressing Real mode memory is the first 1M of the memory system. Real mode memory is the first 1M of the memory system. All real mode addresses are a combination of a segment address plus an offset address. All real mode addresses are a combination of a segment address plus an offset address. The segment address (16-bits) is appended with a 0H or 0000 2 to form a 20-bit address. (or multiplied by 10H) The segment address (16-bits) is appended with a 0H or 0000 2 to form a 20-bit address. (or multiplied by 10H) The effective address is this 20-bit segment address plus a 16-bit offset address. The effective address is this 20-bit segment address plus a 16-bit offset address.

22. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e

23. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e

24. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Defaults Default 16-bit addresses are programs in CS, stack data in SS, and most other data in a program in DS. Default 16-bit addresses are programs in CS, stack data in SS, and most other data in a program in DS. Default 32-bit addresses are programs in CS, stack data in SS and most other data in DS. Default 32-bit addresses are programs in CS, stack data in SS and most other data in DS. What’s the difference? 16-bit addresses use offset addresses in BX, SI, DI, BP, or an offset numeric value. 32-bit addresses use offset addresses in EAX, EBX, ECX, EDX, EBP, EDI, ESI or a numeric value. What’s the difference? 16-bit addresses use offset addresses in BX, SI, DI, BP, or an offset numeric value. 32-bit addresses use offset addresses in EAX, EBX, ECX, EDX, EBP, EDI, ESI or a numeric value. Programs resides in segment CS addressed by IP/EIP Programs resides in segment CS addressed by IP/EIP Stack data resides segment SS addressed by SP/ESP Stack data resides segment SS addressed by SP/ESP

25. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Effective Address Calculations EA = segment x 10H plus offset EA = segment x 10H plus offset (a) 10023 = 10000 + 0023 (b)ABC34 = AAF00 + 0134 (c)21FF0 = 12000 + FFF0 Example (a) contained 1000 in the segment register, example (b) contained a AAF0 in the segment register, and example (c) contained a 1200 in the segment register.

26. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Relocation Segment and offset addressing allows for easy and efficient relocation of code and data. Segment and offset addressing allows for easy and efficient relocation of code and data. To relocate code or data only the segment number needs to be changed. For example, if an instruction appears at offset address 0002 the segment address does not matter because if it changes so does the effective address of he instruction. To relocate code or data only the segment number needs to be changed. For example, if an instruction appears at offset address 0002 the segment address does not matter because if it changes so does the effective address of he instruction.

27. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Levels of Input-Output Level 3: Call a library function (C++, Java) Level 3: Call a library function (C++, Java) easy to do; abstracted from hardware; details hidden easy to do; abstracted from hardware; details hidden slowest performance slowest performance Level 2: Call an operating system function Level 2: Call an operating system function specific to one OS; device-independent specific to one OS; device-independent medium performance medium performance Level 1: Call a BIOS (basic input-output system) function Level 1: Call a BIOS (basic input-output system) function may produce different results on different systems may produce different results on different systems knowledge of hardware required knowledge of hardware required usually good performance usually good performance Level 0: Communicate directly with the hardware Level 0: Communicate directly with the hardware May not be allowed by some operating systems May not be allowed by some operating systems

28. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e Displaying a String of Characters When a HLL program displays a string of characters, the following steps take place:

29. © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.Brey: The Intel Microprocessors, 7e ASM Programming levels ASM programs can perform input-output at each of the following levels: